Semiconductor-on-insulator wafer manufacturing method for reducing light point defects and surface roughness
View Patent ↗A method for reducing light point defects of a semiconductor-on-insulator structure and a method for reducing the surface roughness of a semiconductor-on-insulator structure are disclosed. The methods can include a combination of thermally annealing the structure followed by a non-contact smoothing process.
1. A method for processing a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer, the silicon layer having a cleaved surface defining an outer surface of the structure, the method comprising the steps of:
thermally annealing the structure in an environment comprising a gas selected from the group consisting of argon, hydrogen, helium and mixtures thereof at a temperature of at least about 950° C., wherein the environment contains less than about 10 ppm of oxygen; and
performing a non-contact smoothing process on the cleaved surface.
2. The method of claim 1 , wherein the structure is annealed in a pure argon environment.
3. The method of claim 1 , wherein the structure is annealed at a temperature of from about 1050° C. to about 1200° C.
4. The method of claim 1 , wherein the structure is annealed for a period of from about 15 minutes to about 10 hours.
5. The method of claim 1 , wherein the environment contains less than about 1 ppm of water vapor.
6. The method of claim 1 , wherein the non-contact smoothing process comprises an epi-smoothing process on the cleaved surface.
7. A method for reducing light point defects of a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer, the silicon layer having a cleaved surface defining an outer surface of the structure, the method comprising:
thermally annealing the structure in an environment comprising a gas selected from the group consisting of argon, hydrogen, helium and mixtures thereof at a temperature of at least about 950° C., wherein the environment contains less than about 10 ppm of oxygen; and
performing a non-contact smoothing process on the structure.
8. The method of claim 7 , wherein the structure is annealed in a pure argon environment.
9. The method of claim 7 , wherein the structure is annealed at a temperature of from about 1050° C. to about 1200° C.
10. The method of claim 7 , wherein the structure is annealed for a period of from about 15 minutes to about 10 hours.
11. The method of claim 7 , wherein the environment contains less than about 1 ppm of water vapor.
12. The method of claim 7 , wherein the non-contact smoothing process comprises an epi-smoothing process on the cleaved surface.
13. The method of claim 7 , wherein the method reduces light point defects having a diameter of from about 60 nm to about 70 nm to no more than about 150 per structure.
14. A method for reducing the surface roughness of a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer, the silicon layer having a cleaved surface defining an outer surface of the structure, the method comprising:
thermally annealing the structure in an environment comprising a gas selected from the group consisting of argon, hydrogen, helium and mixtures thereof at a temperature of at least about 950° C., wherein the environment contains less than about 10 ppm of oxygen; and
performing a non-contact smoothing process on the structure.
15. The method of claim 14 , wherein the structure is annealed in a pure argon environment.
16. The method of claim 14 , wherein the structure is annealed at a temperature of from about 1050° C. to about 1200° C.
17. The method of claim 14 , wherein the structure is annealed for a period of from about 15 minutes to about 10 hours.
18. The method of claim 14 , wherein the environment contains less than about 1 ppm of water vapor.
19. The method of claim 14 , wherein the method reduces the Roughness Measurement System roughness of the surface of the structure to below about 0.2 nm as measured with scan sizes of about 1 μm×about 1 μm to about 30 μm×about 30 μm.
20. A method for processing a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer, the silicon layer having a cleaved surface defining an outer surface of the structure, the method comprising the steps of:
thermally annealing the structure in a pure argon environment at a temperature of at least about 950° C., wherein the environment contains less than about 10 ppm of oxygen; and
performing a non-contact smoothing process on the cleaved surface.