Processes and apparatus for preparing heterostructures with reduced strain by radial compression
Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
1. A process for relaxing the strain in a heterostructure comprising a substrate, a surface layer disposed on the substrate and an interface between the substrate and the surface layer, the substrate comprising a central axis, a back surface which is generally perpendicular to the central axis, and a diameter extending across the substrate through the central axis, the process comprising:
forming a dislocation source layer in the substrate; and
subjecting the dislocation source layer to a stress by radially compressing the substrate to generate dislocations and glide the dislocations from the dislocation source layer toward the surface layer.
2. The process as set forth in claim 1 wherein the dislocations are glided to the substrate-surface layer interface and form misfit interfacial dislocations at the interface.
3. The process as set forth in claim 1 wherein the substrate is composed of a material selected from the group consisting of silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenic, indium gallium arsenic or any combination thereof.
4. The process as set forth in claim 1 wherein the surface layer is composed of a material selected from the group consisting of silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide or any combination thereof.
5. The process as set forth in claim 1 wherein the substrate is composed of silicon and the surface layer is composed of gallium nitride.
6. The process as set forth in claim 1 wherein the dislocation source layer is formed by any one of:
slicing the substrate from an ingot comprising semiconductor material;
lapping the back surface of the substrate;
sand blasting the back surface of the substrate
implanting ions into the substrate through the back surface of the substrate.
7. The process as set forth in claim 1 wherein the substrate is heated to at least about 550° C. while radially compressing the heterostructure.
8. The process as set forth in claim 1 wherein a stress is applied to the heterostructure during the radial compression, the stress being at least about 5 MPa.
9. The process as set forth in claim 1 wherein the substrate is radially compressed for a period of at least about 10 seconds.
10. The process as set forth in claim 1 wherein the step of radially compressing the substrate comprises radially compressing the heterostructure.
11. The process as set forth in claim 1 wherein the surface layer is substantially free of threading dislocations.
12. The process as set forth in claim 1 wherein the surface layer continuously extends across the diameter of the substrate.
13. The process as set forth in claim 1 wherein the surface layer comprises discontinuous segments.
14. A process for preparing a relaxed heterostructure, the process comprising:
depositing a surface layer on a front surface of the semiconductor substrate thereby creating a strain between the surface layer and the substrate;
relaxing the strain in the surface layer and the substrate by the process of claim 1 .
15. The process as set forth in claim 14 wherein the semiconductor substrate, has a lattice constant, a S , and the surface layer has a lattice constant, a SL , the ratio of a SL /a S being less than about 1.