IP Library Granted Patent US 8,309,464
Granted Patent B2
US 8,309,464 · App. 12/415,551 · Granted Nov 13, 2012

Methods for etching the edge of a silicon wafer

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Quick Facts
Patent No.
US 8,309,464
App. No.
12/415,551
Granted
Nov 13, 2012
Kind
B2
Abstract

The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Claims (56)

1. A method for removing silicon from a surface of a silicon wafer, the wafer comprising a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a peripheral edge, a radius, R, extending from the central axis to a point along the peripheral edge of the wafer, a nearest peripheral edge point along the peripheral edge of the wafer nearest the central axis, and edge portions of the front and back surfaces of the wafer that extend from the nearest peripheral edge point to a point between the nearest peripheral edge point and the central axis and no more than about 15 mm from the nearest peripheral edge point, the method comprising:

immersing and contacting with an etchant only (i) the peripheral edge of the wafer, (ii) the edge portion of the front surface of the wafer, and (iii) the edge portion of the back surface of the wafer, thereby producing an edge-etched wafer; and

reducing the flatness of the front surface of the edge-etched wafer by more than about 50% by lapping or grinding.

2. The method of claim 1 wherein the edge portions of the front and back surfaces of the wafer extend from the nearest peripheral edge point to a point no more than about 10 mm from the nearest peripheral edge point.

3. The method of claim 1 wherein the edge portions of the front and back surfaces of the wafer extend from the nearest peripheral edge point to a point no more than about 4 mm from the nearest peripheral edge point.

4. The method of claim 1 wherein the edge portions of the front and back surfaces of the wafer extend from the nearest peripheral edge point to a point no more than about 1 mm from the nearest peripheral edge point.

5. The method of claim 1 wherein said contacting occurs prior to reducing the flatness of the front and back surfaces of the wafer by more than about 70%.

6. The method of claim 1 wherein R is at least about 150 mm.

7. The method of claim 1 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant by rotating the wafer.

8. The method of claim 1 wherein the wafer is rotated at a rate of at least about 10 revolutions per minute (rpm).

9. The method of claim 1 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant for at least about 1 minute.

10. The method of claim 1 wherein the rotation of the wafer is reversed to cause the wafer to be rotated in both a clockwise and counter-clockwise rotation while the peripheral edge and front and back edge portions of the wafer are contacted with the etchant.

11. The method of claim 1 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant for a time such that at least about 10 μm, in terms of total thickness, is removed from the front and back edge portions of the wafer.

12. The method of claim 1 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant for a time such that the diameter of the wafer is reduced by at least about 10 μm.

13. The method of claim 1 wherein peripheral edges and edge portions of a plurality of wafers are concurrently contacted with the etchant.

14. The method of claim 1 wherein the etchant is an acidic etchant in the form of an aqueous solution comprising a source of hydrogen ions.

15. The method of claim 14 wherein the etchant comprises a source of hydrogen ions selected from the group consisting of hydrofluoric acid, nitric acid, phosphoric acid, acetic acid, sulfuric acid, hydrochloric acid, citric acid, oxalic acid, propionic acid, permanganic acid, and combinations thereof.

16. The method of claim 14 wherein the etchant further comprises a surfactant selected from the group consisting of ammonium fluoroalkylsulfonate, potassium perfluorooctanesulfonate, dodecylbenzene sulfonic acid alkyl aryl sulfonic acid, and combinations thereof.

17. The method of claim 16 wherein the volumetric ratio of surfactant to the source of hydrogen ions is at least about 0.001:1.

18. The method of claim 1 wherein the etchant is a caustic etchant in the form of an aqueous solution comprising a source of hydroxide ions.

19. The method of claim 18 wherein the source of hydroxide ions is selected from the group consisting of sodium hydroxide, potassium hydroxide, tetramethyl ammonium hydroxide, and combinations thereof.

20. The method of claim 1 further comprising contacting the front surface of the wafer with a caustic etchant to relieve stress in the wafer.

21. The method of claim 20 wherein the caustic etchant removes from about 0.5 μm to about 2 μm of material from the surface of the wafer.

22. The method of claim 1 comprising grinding the front surface and back surface of the edge-etched wafers to reduce the flatness of the wafer.

23. A method for removing silicon from a surface of a silicon wafer, the wafer comprising a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a peripheral edge, a radius, R, extending from the central axis to a point along the peripheral edge of the wafer, a nearest peripheral edge point along the peripheral edge of the wafer nearest the central axis, and edge portions of the front and back surfaces of the wafer that extend from the nearest peripheral edge point to a point between the nearest peripheral edge point and the central axis and no more than about 15 mm from the nearest peripheral edge point, the method comprising:

contacting with an etchant (i) the peripheral edge of the wafer, (ii) the edge portion of the front surface of the wafer, and (iii) the edge portion of the back surface of the wafer, thereby producing an edge-etched wafer; and

reducing the total thickness variation on the front surface of the edge-etched wafer to less than about 20 microns by lapping or grinding.

24. The method of claim 23 wherein R is at least about 150 mm.

25. The method of claim 23 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant by rotating the wafer.

26. The method of claim 23 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant for at least about 1 minute.

27. The method of claim 23 wherein the rotation of the wafer is reversed to cause the wafer to be rotated in both a clockwise and counter-clockwise rotation while the peripheral edge and front and back edge portions of the wafer are contacted with the etchant.

28. The method of claim 23 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant for a time such that at least about 10 μm, in terms of total thickness, is removed from the front and back edge portions of the wafer.

29. The method of claim 23 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant for a time such that the diameter of the wafer is reduced by at least about 10 μm.

30. The method of claim 23 wherein peripheral edges and edge portions of a plurality of wafers are concurrently contacted with the etchant.

31. The method of claim 23 further comprising contacting the front surface of the wafer with a caustic etchant to relieve stress in the wafer.

32. The method of claim 31 wherein the caustic etchant removes from about 0.5 μm to about 2 μm of material from the surface of the wafer.

33. The method of claim 23 comprising grinding the front surface and back surface of the edge-etched wafers to reduce the flatness of the wafer.

34. A method for removing silicon from a surface of a silicon wafer, the wafer comprising a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a peripheral edge, a radius, R, extending from the central axis to a point along the peripheral edge of the wafer, a nearest peripheral edge point along the peripheral edge of the wafer nearest the central axis, and edge portions of the front and back surfaces of the wafer that extend from the nearest peripheral edge point to a point between the nearest peripheral edge point and the central axis and no more than about 15 mm from the nearest peripheral edge point, the method comprising:

contacting with an etchant (i) the peripheral edge of the wafer, (ii) the edge portion of the front surface of the wafer, and (iii) the edge portion of the back surface of the wafer, thereby producing an edge-etched wafer; and

reducing the total thickness variation of the edge-etched wafer to less than about 3 microns by lapping or grinding.

35. The method of claim 34 wherein R is at least about 150 mm.

36. The method of claim 34 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant by rotating the wafer.

37. The method of claim 34 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant for at least about 1 minute.

38. The method of claim 34 wherein the rotation of the wafer is reversed to cause the wafer to be rotated in both a clockwise and counter-clockwise rotation while the peripheral edge and front and back edge portions of the wafer are contacted with the etchant.

39. The method of claim 34 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant for a time such that at least about 10 μm, in terms of total thickness, is removed from the front and back edge portions of the wafer.

40. The method of claim 34 wherein the peripheral edge and front and back edge portions of the wafer are contacted with the etchant for a time such that the diameter of the wafer is reduced by at least about 10 μm.

41. The method of claim 34 wherein peripheral edges and edge portions of a plurality of wafers are concurrently contacted with the etchant.

42. The method of claim 34 further comprising contacting the front surface of the wafer with a caustic etchant to relieve stress in the wafer.

43. The method of claim 42 wherein the caustic etchant removes from about 0.5 μm to about 2 μm of material from the surface of the wafer.

44. The method of claim 34 comprising grinding the front surface and back surface of the edge-etched wafers to reduce the flatness of the wafer.

45. A method for removing silicon from a surface of a silicon wafer, the wafer comprising a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a peripheral edge, a radius, R, extending from the central axis to a point along the peripheral edge of the wafer, and a nearest peripheral edge point along the peripheral edge of the wafer nearest the central axis, and edge portions of the front and back surfaces of the wafer that extend from the nearest peripheral edge point to a point between the nearest peripheral edge point and the central axis and no more than about 15 mm from the nearest peripheral edge point, the method comprising:

contacting with an etchant (i) the peripheral edge of the wafer, (ii) the edge portion of the front surface of the wafer, (iii) the edge portion of the back surface of the wafer, thereby producing an edge-etched wafer;

reducing the flatness of the edge-etched wafer by at least about 50%;

contacting the peripheral edge, front surface, and back surface of the edge-etched wafer with a caustic etchant in the form of an aqueous solution comprising a source of hydroxide ions;

polishing the front surface and back surface of the edge-etched wafer; and

polishing the peripheral edge of the edge-etched wafer.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: SUNEDISON SEMICONDUCTOR LIMITED; MEMC JAPAN LIMITED; MEMC ELECTRONIC MATERIALS S.P.A.
To: GLOBALWAFERS CO., LTD.
Reel/Frame 046327/0001 →
NOTICE OF LICENSE AGREEMENT Recorded Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
RELEASE OF SECURITY INTEREST Recorded Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
SECURITY AGREEMENT Recorded Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: BANK OF AMERICA, N.A.
To: ENFLEX CORPORATION; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0031 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: GOLDMAN SACHS BANK USA
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0092 →
SECURITY AGREEMENT Recorded Oct 1, 2012
From: NVT, LLC; SUN EDISON LLC; SOLAICX, INC.; MEMC ELECTRONIC MATERIALS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 029057/0810 →
SECURITY AGREEMENT Recorded Apr 1, 2011
From: MEMC ELECTRONIC MATERIALS, INC.; SUNEDISON LLC; SOLAICX
To: BANK OF AMERICA, N.A.
Reel/Frame 026064/0720 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2009
From: ERK, HENRY F.; ALBRECHT, PETER D.; HOLLANDER, EUGENE R.; DOANE, THOMAS E.; SCHMIDT, JUDITH A.; VANDAMME, ROLAND R.; ZHANG, GUOQIANG (DAVID)
To: MEMC ELECTRONIC MATERIALS, INC.
Reel/Frame 022560/0266 →