IP Library Granted Patent US 8,192,822
Granted Patent B2
US 8,192,822 · App. 12/415,555 · Granted Jun 5, 2012

Edge etched silicon wafers

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,192,822
App. No.
12/415,555
Granted
Jun 5, 2012
Kind
B2
Abstract

The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Claims (27)

1. A silicon wafer comprising a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a radius, R, extending from the central axis to a point along the peripheral edge, a point along the peripheral edge nearest the central axis, edge portions of the front and back surfaces of the wafer that extend from the nearest peripheral edge point to a point between the nearest peripheral point and the central axis and no more than about 15 mm from the nearest peripheral edge point, and central portions of the front and back surfaces of the wafer that extend from the point between the nearest peripheral point and the central axis and the central axis; wherein:

the front and back surfaces of the wafer have a total thickness variation of at least 20 microns;

the central portions of the front and back surfaces of the wafer have a surface roughness of at least about 0.3 μm Ra; and

the edge portions of the front and back surfaces of the wafer have a surface roughness of less than about 0.3 μm Ra, the central portions of the front and back surfaces of the wafer having a surface roughness greater than the surface roughness of the edge portions of the front and back surface of the wafer.

2. The silicon wafer of claim 1 wherein the front and back surfaces of the wafer have a total thickness variation of at least about 25 microns.

3. The silicon wafer of claim 1 wherein the front and back surfaces of the wafer have a total thickness variation of at least about 35 microns.

4. The silicon wafer of claim 1 wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 0.3 to about 2.5 μm Ra.

5. The silicon wafer of claim 1 wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 0.7 to about 2 μm Ra.

6. The silicon wafer of claim 1 wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 1 to about 1.5 μm Ra.

7. The silicon wafer of claim 1 wherein the edge portions of the front and back surfaces of the wafer have a surface roughness of from about 0.2 μm Ra.

8. The silicon wafer of claim 1 wherein the edge portions of the front and back surfaces of the wafer have a surface roughness of from about 0.1 μm Ra.

9. The silicon wafer of claim 1 wherein R is at least about 150 mm.

10. The silicon wafer of claim 1 wherein the peripheral edge comprises two bevels and an apex.

11. The silicon wafer of claim 1 wherein the peripheral edge is rounded.

12. A silicon wafer comprising a central axis, a front surface and a back surface that are generally perpendicular to the central axis, a radius, R, extending from the central axis to a point along the peripheral edge, a point along the peripheral edge nearest the central axis, edge portions of the front and back surfaces of the wafer that extend from the nearest peripheral edge point to a point between the nearest peripheral point and the central axis, and central portions of the front and back surfaces of the wafer that extend from the point between the nearest peripheral point and the central axis and the central axis; wherein:

the front and back surfaces of the wafer have a total thickness variation of at least 20 microns;

the central portions of the front and back surfaces of the wafer have a surface roughness of at least about 0.3 μm Ra; and

the edge portions of the front and back surfaces of the wafer have a surface roughness of less than about 0.2 μm Ra.

13. The silicon wafer of claim 12 wherein the front and back surfaces of the wafer have a total thickness variation of at least about 25 microns.

14. The silicon wafer of claim 12 wherein the front and back surfaces of the wafer have a total thickness variation of at least about 35 microns.

15. The silicon wafer of claim 12 wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 0.3 to about 2.5 μm Ra.

16. The silicon wafer of claim 12 wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 0.7 to about 2 μm Ra.

17. The silicon wafer of claim 12 wherein the central portions of the front and back surfaces of the wafer have a surface roughness of from about 1 to about 1.5 μm Ra.

18. The silicon wafer of claim 12 wherein the edge portions of the front and back surfaces of the wafer have a surface roughness of from about 0.1 μm Ra.

19. The silicon wafer of claim 12 wherein R is at least about 150 mm.

20. The silicon wafer of claim 12 wherein the peripheral edge comprises two bevels and an apex.

21. The silicon wafer of claim 12 wherein the peripheral edge is rounded.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: SUNEDISON SEMICONDUCTOR LIMITED; MEMC JAPAN LIMITED; MEMC ELECTRONIC MATERIALS S.P.A.
To: GLOBALWAFERS CO., LTD.
Reel/Frame 046327/0001 →
NOTICE OF LICENSE AGREEMENT Recorded Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
RELEASE OF SECURITY INTEREST Recorded Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
SECURITY AGREEMENT Recorded Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: BANK OF AMERICA, N.A.
To: ENFLEX CORPORATION; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0031 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: GOLDMAN SACHS BANK USA
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0092 →
SECURITY AGREEMENT Recorded Oct 1, 2012
From: NVT, LLC; SUN EDISON LLC; SOLAICX, INC.; MEMC ELECTRONIC MATERIALS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 029057/0810 →
SECURITY AGREEMENT Recorded Apr 1, 2011
From: MEMC ELECTRONIC MATERIALS, INC.; SUNEDISON LLC; SOLAICX
To: BANK OF AMERICA, N.A.
Reel/Frame 026064/0720 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2009
From: ERK, HENRY F.; ALBRECHT, PETER D.; HOLLANDER, EUGENE R.; DOANE, THOMAS E.; SCHMIDT, JUDITH A.; VANDAMME, ROLAND R.; ZHANG, GUOQIANG (DAVID)
To: MEMC ELECTRONIC MATERIALS, INC.
Reel/Frame 022560/0473 →