Methods for generating representations of flatness defects on wafers
View Patent ↗Methods are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.
1. A method of generating a representation of flatness defects on a substrate, the method comprising:
receiving data describing the thickness of the substrate at a plurality of points on the substrate, the substrate divided into a plurality of sites;
defining a reference plane for each of the plurality of sites;
defining, for each of the sites, a lower plane spaced from the reference plane towards a back side of the substrate by a threshold value and an upper plane spaced from the reference plane away from the back side of the substrate by the threshold value;
determining, with a processor, which of the plurality of points on the substrate represents a flatness defect by identifying which of the plurality of points are not disposed between the upper plane and the lower plane; and
generating, with the processor, a graphical representation depicting a location of each of the flatness defects on the substrate, wherein generating the graphical representation of the flatness defects includes differentiating in the graphical representation between points having flatness defects disposed between the lower plane and the back side of the substrate and points having flatness defects disposed above the upper plane.
2. The method of claim 1 wherein defining the reference plane for each of the plurality of sites includes applying a least squares algorithm to the received data.
3. The method of claim 1 wherein the plurality of sites are equally sized and abut each other.
4. The method of claim 1 further comprising generating a graphical representation of the flatness defects for a plurality of substrates.
5. The method of claim 1 further comprising, before the substrate is divided into a plurality of sites, defining an edge exclusion zone adjacent a circumferential edge of the substrate.
6. The method of claim 5 further comprising dividing the substrate into the plurality of equally sized sites except portions of the substrate where a site would have a geometric center disposed in the edge exclusion zone.
7. The method of claim 1 further comprising altering a substrate processing method based on the graphical representation depicting the location of each of the flatness defects on the substrate.
8. The method of claim 7 wherein the substrate is a semiconductor wafer.
9. A method of generating a graphical representation of flatness defects on a wafer, the method comprising:
(i) defining an edge exclusion zone disposed adjacent a circumferential edge of the wafer;
(ii) dividing the wafer into a plurality of equally sized sites, except portions of the wafer where a geometric center of the site would be disposed in the edge exclusion zone;
(iii) receiving data describing the thickness of the wafer at a plurality of points on the wafer, at least some points disposed in each of the plurality of sites;
(iv) defining a reference plane for each of the plurality of sites;
(v) defining, for each of the sites, a lower plane spaced from the reference plane towards a back side of the wafer by a threshold value and an upper plane spaced from the reference plane away from the back side of the wafer by the threshold value;
(vi) determining, with a processor, which of the plurality of points on the wafer represents a flatness defect by identifying which of the plurality of points are not disposed between the upper plane and the lower plane; and
(vii) generating, with the processor, a graphical representation depicting a location of each of the flatness defects on the wafer, wherein generating the graphical representation depicting the location of each of the flatness defects on the wafer includes graphically differentiating in the graphical representation between points having flatness defects disposed between the lower plane and the back side of the wafer and points having flatness defects disposed above the upper plane.
10. The method of claim 9 further comprising repeating steps (i) through (vii) for each of a plurality of wafers.
11. The method of claim 10 further comprising merging each of generated graphical representations for each of the plurality of the wafers into a single combined graphical representation.
12. The method of claim 9 further comprising altering a wafer processing method based on the graphical representation depicting the location of each of the flatness defects on the wafer.
13. A method of generating a graphical representation of flatness defects on a plurality of wafers, the method comprising:
(i) receiving data describing the thickness of one of the plurality of wafers at a plurality of points on the wafer, at least some points disposed in each of a plurality of equally sized sites;
(ii) defining a reference plane for each of the plurality of sites;
(iii) defining, for each of the sites, a lower plane spaced from the reference plane towards a back side of the wafer by a threshold value and an upper plane spaced from the reference plane away from the back side of the wafer by the threshold value;
(iv) determining, with a processor, which of the plurality of points on the wafer represents a flatness defect by identifying which of the plurality of points are not disposed between the upper plane and the lower plane;
(v) repeating steps (i) through (iv) for each of the plurality of wafers; and
(vi) generating, with the processor, a graphical representation depicting a location of each of the flatness defects on the plurality of wafers, wherein generating the graphical representation depicting the location of each of the flatness defects on the plurality of wafers includes graphically differentiating in the graphical representation between points having flatness defects disposed between the lower plane and the back side of the wafer and points having flatness defects disposed above the upper plane.
14. The method of claim 13 further comprising altering a wafer processing method based on the generated graphical representation depicting the location of each of flatness defects on the plurality of wafers.
15. The method of claim 14 wherein altering the wafer processing method includes at least one of: extending the duration of a processing step, reducing the duration of a processing step, eliminating a processing step, adding an additional processing step, and modifying a processing step.
16. A method of generating a graphical representation of flatness defects on a wafer, the method comprising:
(i) defining an edge exclusion zone disposed adjacent a circumferential edge of the wafer;
(ii) dividing the wafer into a plurality of equally sized sites, except portions of the wafer where a geometric center of the site would be disposed in the edge exclusion zone;
(iii) receiving data describing the thickness of the wafer at a plurality of points on the wafer, at least some points disposed in each of the plurality of sites;
(iv) defining a reference plane for each of the plurality of sites;
(v) defining, for each of the sites, a lower plane spaced from the reference plane towards a back side of the wafer by a threshold value and an upper plane spaced from the reference plane away from the back side of the wafer by the threshold value;
(vi) determining, with a processor, which of the plurality of points on the wafer represents a flatness defect by identifying which of the plurality of points are not disposed between the upper plane and the lower plane;
(vii) generating, with the processor, a graphical representation depicting a location of each of the flatness defects on the wafer;
(viii) repeating steps (i) through (vii) for each of a plurality of wafers; and
(ix) merging each of the generated graphical representations for each of the plurality of wafers into a single combined graphical representation.