Methods for producing low oxygen silicon ingots
An method for producing a silicon ingot includes melting polycrystalline silicon in a crucible enclosed in a vacuum chamber to form a melt, generating a cusped magnetic field within the vacuum chamber, dipping a seed crystal into the melt, withdrawing the seed crystal from the melt to pull a single crystal that forms the silicon ingot, wherein the silicon ingot has a diameter greater than about 150 millimeters (mm), and simultaneously regulating a plurality of process parameters such that the silicon ingot has an oxygen concentration less than about 5 parts per million atoms (ppma). The plurality of process parameters include a wall temperature of the crucible, a transport of silicon monoxide (SiO) from the crucible to the single crystal, and an evaporation rate of SiO from the melt.
1. A method for producing a silicon ingot, the method comprising:
melting polycrystalline silicon in a crucible enclosed in a vacuum chamber to form a melt;
generating a cusped magnetic field within the vacuum chamber;
dipping a seed crystal into the melt; withdrawing the seed crystal from the melt to pull a single crystal that forms the silicon ingot, wherein the silicon ingot has a diameter greater than about 150 millimeters (mm); and
simultaneously regulating a plurality of process parameters such that the silicon ingot has an oxygen concentration less than about 5 parts per million atoms (ppma), wherein the plurality of process parameters include a wall temperature of the crucible, a transport of silicon monoxide (SiO) from the crucible to the single crystal, and an evaporation rate of SiO from the melt; wherein simultaneously regulating a plurality of process parameters comprises maintaining a melt to reflector gap in a range from approximately 60 mm to 80 mm, and
wherein the silicon ingot has a diameter in a range from approximately 150 mm to 460 mm.
2. A method in accordance with claim 1 , wherein the silicon ingot has a diameter of approximately 300 mm.
3. The method in accordance with claim 1 , wherein simultaneously regulating a plurality of process parameters comprises operating a heater positioned below the crucible.
4. A method in accordance with claim 1 , wherein simultaneously regulating a plurality of process parameters comprises rotating the crucible at a rate in a range from approximately 1.3 rpm to 2.2 rpm.
5. A method in accordance with claim 1 , wherein generating a cusped magnetic field comprises generating a cusped magnetic field having a magnetic field strength in a range from approximately 0.02 to 0.05 Tesla at an edge of the single crystal at a melt-solid interface, and having a magnetic field strength in a range from approximately 0.05 to 0.12 Tesla at a wall of the crucible.
6. A method in accordance with claim 1 , wherein simultaneously regulating a plurality of process parameters comprises flowing argon gas through the vacuum chamber at a flow rate in a range from approximately 100 standard liters per minute (slpm) to 150 slpm.
7. A method in accordance with claim 1 , wherein simultaneously regulating a plurality of process parameters comprises flowing argon gas through the vacuum chamber at a pressure in a range from approximately 10 torr to 30 torr.
8. A method in accordance with claim 1 , wherein the measured defects include less than 400 defects having a size less than 60 nm, less than 100 defects having a size between 60 and 90 nm, and less than 100 defects having a size between 90 and 120 nm.
9. A method in accordance with claim 8 , wherein doping the single crystal comprises doping the single crystal with nitrogen such that a nitrogen concentration is within a range from 0 atoms per cubic centimeter to 8e15 atoms per cubic centimeter.
10. A wafer in accordance with claim 1 , wherein the wafer has 30 ohm-cm to 300 ohm-centimeter N-type resistivity such that the wafer is suitable for use in IGBT applications.
11. A wafer in accordance with claim 1 , wherein the wafer has greater than 750 ohm-cm N/P-type resistivity such that the wafer is suitable for use in IGBT applications.
12. A wafer in accordance with claim 1 , wherein the wafer has greater than 750 ohm-cm P-type resistivity such that the wafer is suitable for use in RF, HR-SOI, and CTL-SOI applications.
13. A wafer in accordance with claim 1 , wherein the wafer is a handle wafer.
14. A wafer in accordance with claim 1 , wherein the wafer is a P-type product having at least one of boron, aluminum, germanium, and indium as a majority carrier, and having at least one of red phosphorus, phosphorus, arsenic, and antimony as a minority carrier.
15. A wafer in accordance with claim 1 , wherein the wafer is a N-type product having at least one red phosphorus, phosphorus, arsenic, and antimony as a majority carrier, and having at least one of boron, aluminum, germanium, and indium as a minority carrier.
16. A method for producing a silicon ingot, the method comprising:
melting polycrystalline silicon in a crucible enclosed in a vacuum chamber to form a melt;
generating a cusped magnetic field within the vacuum chamber;
dipping a seed crystal into the melt; withdrawing the seed crystal from the melt to pull a single crystal that forms the silicon ingot, wherein the silicon ingot has a diameter greater than about 150 millimeters (mm); and
simultaneously regulating a plurality of process parameters such that the silicon ingot has an oxygen concentration less than about 5 parts per million atoms (ppma), wherein the plurality of process parameters include a wall temperature of the crucible, a transport of silicon monoxide (SiO) from the crucible to the single crystal, and an evaporation rate of SiO from the melt; wherein simultaneously regulating a plurality of process parameters comprises positioning a cusp of the generated magnetic field in a range from approximately 10 mm to 40 mm below a surface of the melt, and
wherein the silicon ingot has a diameter in a range from approximately 150 mm to 460 mm.
17. A method in accordance with claim 16 , wherein the silicon ingot has a diameter of approximately 300 mm.
18. The method in accordance with claim 16 , wherein simultaneously regulating a plurality of process parameters comprises operating a heater positioned below the crucible at a power in a range from approximately 0 kilowatts to 5 kilowatts.
19. A method in accordance with claim 16 , wherein simultaneously regulating a plurality of process parameters comprises rotating the crucible at a rate in a range from approximately 1.3 rpm to 2.2 rpm.
20. A method in accordance with claim 16 , wherein generating a cusped magnetic field comprises generating a cusped magnetic field having a magnetic field strength in a range from approximately 0.02 to 0.05 Tesla at an edge of the single crystal at a melt-solid interface, and having a magnetic field strength in a range from approximately 0.05 to 0.12 Tesla at a wall of the crucible.
21. A method in accordance with claim 16 , wherein simultaneously regulating a plurality of process parameters comprises flowing argon gas through the vacuum chamber at a flow rate in a range from approximately 100 standard liters per minute (slpm) to 150 slpm.
22. A method in accordance with claim 16 , wherein simultaneously regulating a plurality of process parameters comprises flowing argon gas through the vacuum chamber at a pressure in a range from approximately 10 torr to 30 torr.
23. A method in accordance with claim 16 , wherein the measured defects include less than 400 defects having a size less than 60 nm, less than 100 defects having a size between 60 and 90 nm, and less than 100 defects having a size between 90 and 120 nm.
24. A method in accordance with claim 23 , wherein doping the single crystal comprises doping the single crystal with nitrogen such that a nitrogen concentration is within a range from 0 atoms per cubic centimeter to 8e15 atoms per cubic centimeter.
25. A method in accordance with claim 16 , wherein simultaneously regulating a plurality of process parameters comprises maintaining a melt to reflector gap in a range from approximately 60 mm to 80 mm.
26. A wafer in accordance with claim 16 , wherein the wafer has 30 ohm-cm to 300 ohm-centimeter N-type resistivity such that the wafer is suitable for use in IGBT applications.
27. A wafer in accordance with claim 16 , wherein the wafer has greater than 750 ohm-cm N/P-type resistivity such that the wafer is suitable for use in IGBT applications.
28. A wafer in accordance with claim 16 , wherein the wafer has greater than 750 ohm-cm P-type resistivity such that the wafer is suitable for use in RF, HR-SOI, and CTL-SOI applications.
29. A wafer in accordance with claim 16 , wherein the wafer is a handle wafer.
30. A wafer in accordance with claim 16 , wherein the wafer is a P-type product having at least one of boron, aluminum, germanium, and indium as a majority carrier, and having at least one of red phosphorus, phosphorus, arsenic, and antimony as a minority carrier.
31. A wafer in accordance with claim 16 , wherein the wafer is a N-type product having at least one red phosphorus, phosphorus, arsenic, and antimony as a majority carrier, and having at least one of boron, aluminum, germanium, and indium as a minority carrier.