IP Library Granted Patent US 8,859,393
Granted Patent B2
US 8,859,393 · App. 13/162,122 · Granted Oct 14, 2014

Methods for in-situ passivation of silicon-on-insulator wafers

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Quick Facts
Patent No.
US 8,859,393
App. No.
13/162,122
Granted
Oct 14, 2014
Kind
B2
Abstract

Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.

Claims (8)

1. A Method for performing a passivation process on a silicon-on-insulator wafer in a chamber, the method comprising the steps of:

cleaving a bonded wafer pair within the chamber to form the silicon-on-insulator (SOI) wafer, the SOI wafer having a cleaved surface;

passivating the cleaved surface of the SOI wafer in-situ by exposing the cleaved surface to a gaseous form of ozone, wherein exposing the cleaved surface to the gaseous form of ozone result in a thin layer of oxide on the cleaved surface and wherein the ozone is introduced into the chamber after the bonded wafer pair has been cleaved, and no intermediate steps are performed between cleaving and passivating; and

removing the silicon-on-insulator wafer from the chamber.

2. The method of claim 1 wherein the thin layer of oxide formed on the cleaved surface of the silicon-on-insulator structure is formed to prevent contaminants from reacting with the cleaved surface.

3. The method of claim 1 wherein passivating the cleaved surface of the silicon-on-insulator wafer in-situ comprises passivating the cleaved surface in the chamber in which the bonded wafer pair is cleaved to form the silicon-on-insulator wafer.

4. The method of claim 3 further comprising forming the bonded wafer pair within the same chamber in which the bonded wafer is later cleaved.

5. The method of claim 1 wherein cleaving and separating the bonded wafer pair along a cleave plane is initiated and propagated by mechanical force.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: SUNEDISON SEMICONDUCTOR LIMITED; MEMC JAPAN LIMITED; MEMC ELECTRONIC MATERIALS S.P.A.
To: GLOBALWAFERS CO., LTD.
Reel/Frame 046327/0001 →
NOTICE OF LICENSE AGREEMENT Recorded Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
RELEASE OF SECURITY INTEREST Recorded Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
SECURITY AGREEMENT Recorded Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: GOLDMAN SACHS BANK USA
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0092 →
SECURITY AGREEMENT Recorded Oct 1, 2012
From: NVT, LLC; SUN EDISON LLC; SOLAICX, INC.; MEMC ELECTRONIC MATERIALS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 029057/0810 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2011
From: RIES, MICHAEL J.; WITTE, DALE A.; STEFANESCU, ANCA; JONES, ANDREW M.
To: MEMC ELECTRONIC MATERIALS, INC.
Reel/Frame 026459/0603 →