High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss

1. A method of forming a multilayer structure, the method comprising:

forming a crystalline semiconductor nitride layer on a front surface of a silicon wafer handle substrate, wherein the crystalline semiconductor nitride layer is selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof and further wherein the crystalline semiconductor nitride layer is formed by metalorganic chemical vapor deposition occurring by a reaction between an organic compound or a metalorganic compound and a nitrogen-containing precursor and wherein the silicon wafer handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the silicon wafer handle substrate and the other of which is a back surface of the silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the silicon wafer handle substrate, and a bulk region between the front and back surfaces of the silicon wafer handle substrate, wherein the silicon wafer handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;

forming a silicon dioxide layer having a thickness between about 500 nanometers and about 2 micrometers in interfacial contact with the crystalline semiconductor nitride layer; and

bonding a dielectric layer in interfacial contact with a front surface of a semiconductor donor substrate to the silicon dioxide layer in interfacial contact with the crystalline semiconductor nitride layer to thereby form a bonded structure, wherein the semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate.

2. The method of claim 1 wherein the silicon wafer handle substrate is sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

3. The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 500 Ohm-cm and about 100,000 Ohm-cm.

4. The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 1000 Ohm-cm and about 100,000 Ohm-cm.

5. The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 1000 Ohm-cm and about 10,000 Ohm-cm.

6. The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 2000 Ohm-cm and about 10,000 Ohm-cm.

7. The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 10,000 Ohm-cm.

8. The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 5,000 Ohm-cm.

9. A method of forming a multilayer structure, the method comprising:

forming an amorphous semiconductor nitride layer on a front surface of a silicon wafer handle substrate, wherein the amorphous semiconductor nitride is selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof and further wherein the amorphous semiconductor nitride layer is formed by metalorganic chemical vapor deposition occurring by a reaction between an organic compound or a metalorganic compound and a nitrogen-containing precursor and wherein the silicon wafer handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the silicon wafer handle substrate and the other of which is a back surface of the silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the silicon wafer handle substrate, and a bulk region between the front and back surfaces of the silicon wafer handle substrate, wherein the silicon wafer handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm:

forming a silicon dioxide layer having a thickness between about 500 nanometers and about 2 micrometers in interfacial contact with the amorphous semiconductor nitride layer; and

bonding a dielectric layer in interfacial contact with a front surface of a semiconductor donor substrate to the silicon dioxide layer in interfacial contact with the crystalline semiconductor nitride layer to thereby form a bonded structure, wherein the semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate.

10. The method of claim 1 wherein the crystalline semiconductor nitride layer comprises aluminum nitride.

11. The method of claim 1 wherein the crystalline semiconductor nitride layer comprises boron nitride.

12. The method of claim 1 wherein the crystalline semiconductor nitride layer comprises indium nitride.

13. The method of claim 1 wherein the crystalline semiconductor nitride layer comprises gallium nitride.

14. The method of claim 1 wherein the crystalline semiconductor nitride layer has an average thickness of between about 1 nanometer and about 2000 nanometers.

15. The method of claim 1 wherein the crystalline semiconductor nitride layer has an average thickness of between about 5 nanometers and about 1000 nanometers.

16. The method of claim 1 wherein the crystalline semiconductor nitride layer has an average thickness of between about 5 nanometers and about 500 nanometers.

17. The method of claim 1 wherein the crystalline semiconductor nitride layer has an average thickness of between about 5 nanometers and about 200 nanometers.

18. The method of claim 1 wherein the semiconductor donor substrate comprises a silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

19. The method of claim 1 wherein the semiconductor donor substrate comprises a silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method.

20. The method of claim 1 wherein the dielectric layer in interfacial contact with the semiconductor donor substrate is selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and any combination thereof.

21. The method of claim 1 further comprising heating the bonded structure at a temperature and for a duration sufficient to strengthen the bond between the dielectric layer in interfacial contact with the semiconductor donor structure and silicon dioxide layer in interfacial contact with the crystalline semiconductor nitride layer.

22. The method of claim 1 wherein the semiconductor donor substrate comprises an ion implanted damage layer.

23. The method of claim 22 further comprising mechanically cleaving the bonded structure at the ion implanted damage layer of the semiconductor donor substrate to thereby prepare a cleaved structure comprising the silicon wafer handle substrate, the crystalline semiconductor nitride layer in contact with the front surface of the silicon wafer handle substrate, the silicon dioxide layer in interfacial contact with the crystalline semiconductor nitride layer, the dielectric layer in contact with the silicon dioxide layer, and a semiconductor device layer in contact with the dielectric layer.

24. The method of claim 23 further comprising heating the cleaved structure at a temperature and for a duration sufficient to strengthen the bond between the dielectric layer and the silicon dioxide layer.