Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
View Patent ↗A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
1. A process for heat-treating a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method to influence the precipitation behavior of oxygen in the single crystal silicon wafer in a subsequent thermal processing step, the single crystal silicon wafer having a front surface, a back surface, a central plane between the front and back surfaces, a front surface layer which comprises the region of a wafer between the front surface and a depth, D 1 , measured from the front surface and toward the central plane, a bulk layer which comprises the region of the wafer between the central plane and front surface layer, is doped with arsenic or phosphorous, and has a resistivity of less than about 5 mΩ-cm, the process comprising:
heat-treating the single crystal silicon wafer in an atmosphere comprising a nitrogen-containing gas to increase a density of crystal lattice vacancies in the wafer bulk; and
cooling the heat-treated single crystal silicon wafer such that the wafer bulk is supersaturated with crystal lattice vacancies.
2. The process for heat-treating a single crystal silicon wafer according to claim 1 wherein subjecting the cooled wafer to an oxygen precipitation heat-treatment at a temperature in excess of about 700° C. causes the formation of oxygen precipitates in the bulk layer.
3. The process for heat-treating a single crystal silicon wafer according to claim 2 wherein the oxygen precipitation heat-treatment step causes the formation of oxygen precipitates at a density of at least about 1×10 7 cm −3 .
4. The process for heat-treating a single crystal silicon wafer according to claim 2 wherein the oxygen precipitation heat-treatment step causes the formation of oxygen precipitates at a density of at least about 1×10 8 cm −3 .
5. The process for heat-treating a single crystal silicon wafer according to claim 2 wherein the oxygen precipitation heat-treatment step causes the formation of oxygen precipitates at a density of at least about 1×10 9 cm −3 .
6. The process for heat-treating a single crystal silicon wafer according to claim 1 wherein the atmosphere comprising the nitrogen-containing gas comprises nitrogen or ammonia.
7. The process for heat-treating a single crystal silicon wafer according to claim 1 wherein heat-treating the single crystal silicon wafer comprises heating the wafer to a temperature of at least about 1200° C. at a heating rate of at least about 10° C/sec and maintaining the wafer at that temperature for a period of at least about 1 second and less than about 60 seconds.
8. The process for heat-treating a single crystal silicon wafer according to claim 7 wherein the heating rate is at least about 60° C/sec.
9. The process for heat-treating a single crystal silicon wafer according to claim 1 wherein heat-treating the single crystal silicon wafer comprises heating the wafer to a temperature of at least about 1230° C. at a heating rate of at least about 10° C/sec and maintaining the wafer at that temperature for a period of at least about 1 second and less than about 60 seconds.
10. The process for heat-treating a single crystal silicon wafer according to claim 9 wherein the heating rate is at least about 60° C/sec.
11. The process for heat-treating a single crystal silicon wafer according to claim 1 wherein heat-treating the single crystal silicon wafer comprises heating the wafer to a temperature of at least about 1230° C. at a heating rate of at least about 10° C/sec and maintaining the wafer at that temperature for a period of about 15 seconds.
12. The process for heat-treating a single crystal silicon wafer according to claim 11 wherein the heating rate is at least about 60° C/sec.
13. The process for heat-treating a single crystal silicon wafer according to claim 1 wherein the heat-treated wafer is cooled at a rate of at least about 20° C/second through the temperature range in which crystal lattice vacancies are relatively mobile in silicon.
14. The process for heat-treating a single crystal silicon wafer according to claim 1 wherein the heat-treated wafer is cooled at a rate of at least about 50° C/second through the temperature range in which crystal lattice vacancies are relatively mobile in silicon.
15. The process for heat-treating a single crystal silicon wafer according to claim 1 wherein the heat-treated wafer is cooled at a rate of at least about 100° C/second through the temperature range in which crystal lattice vacancies are relatively mobile in silicon.
16. The process for heat-treating a single crystal silicon wafer according to claim 1 wherein the wafer is a substrate for epitaxy and the process further comprises the step of depositing an epitaxial layer on the front surface of the wafer.
17. The process for heat-treating a single crystal silicon wafer according to claim 16 wherein the epitaxial layer is deposited after the heat-treating step.
18. The process for heat-treating a single crystal silicon wafer according to claim 16 wherein the depositing an epitaxial layer comprises the step of:
exposing the wafer to an atmosphere comprising SiHCl 3 , H 2 , and PH 3 .