IP Library Granted Patent US 9,588,891
Granted Patent B2
US 9,588,891 · App. 14/835,392 · Granted Mar 7, 2017

Managing cache pools

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Quick Facts
Patent No.
US 9,588,891
App. No.
14/835,392
Granted
Mar 7, 2017
Kind
B2
Abstract

Apparatuses, systems, and methods are disclosed for managing cache pools. A storage request module monitors storage requests received by a cache. The storage requests include read requests and write requests. A read pool module adjusts a size of a read pool of the cache to increase a read hit rate of the storage requests. A dirty write pool module adjusts a size of a dirty write pool of the cache to increase a dirty write hit rate of the storage requests.

Claims (34)

1. A method comprising:

monitoring storage requests received by a cache, the storage requests comprising read requests and write requests;

dynamically adjusting a size of a read pool of the cache to increase a read hit rate of the storage requests, wherein the read pool comprises a recent read pool and a frequent read pool; and

dynamically adjusting a size of a dirty write pool of the cache to increase a dirty write hit rate of the storage requests, wherein dynamically adjusting the size of the read pool and the dirty write pool comprises reducing a target pool size.

2. The method of claim 1 , wherein dynamically adjusting the size of the read pool further comprises increasing a target recent read pool size of the recent read pool in response to a read hit in the recent read pool, the requested data transitioning from the recent read pool to the frequent read pool in response to a frequent read threshold number of read hits for the requested data in the recent read pool.

3. The method of claim 1 , further comprising transitioning data from the recent read pool to the frequent read pool in response to a frequent read threshold number of read hits.

4. The method of claim 1 , wherein reducing the target pool size comprises reducing the target pool size in response to a miss for a corresponding one of the read pool and the dirty write pool.

5. The method of claim 1 , wherein dynamically adjusting the size of the read pool further comprises dynamically adjusting a size of the recent read pool and a size of the frequent read pool.

6. An apparatus comprising:

a storage request module configured to monitor storage requests received by a cache, the storage requests comprising read requests and write requests;

a read pool module configured to determine a target read pool size for a read pool of the cache to increase a read hit rate of the storage requests, wherein determining the target read pool size comprises reducing the target read pool size in response to a read miss;

a dirty write pool module configured to determine a target dirty write pool size for a dirty write pool of the cache to increase a dirty write hit rate of the storage requests; and

a destage module configured to adjust a destage rate for destaging dirty write data from the dirty write pool of the cache, wherein the dirty write pool module sets the destage rate so that the size of the dirty write pool is within a predetermined threshold.

7. The apparatus of claim 6 , wherein the destage module transitions from a write-back to a write-through write policy in response to a predetermined condition.

8. The apparatus of claim 6 , wherein the destage module comprises a write-back write policy, and does not immediately write data of a write request.

9. The apparatus of claim 6 , wherein the destage module writes back data when a storage capacity in the cache falls below a predetermined threshold to satisfy a destaging pressure.

10. The apparatus of claim 6 , wherein the apparatus virtually stripes cached data across multiple caches.

11. The apparatus of claim 6 , wherein the cache switches operation from a first mode to a second mode.

12. The apparatus of claim 11 , wherein the cache operates in the second mode for a predetermined period of time.

13. The apparatus of claim 11 , wherein the second mode comprises one of a write-back mode and a write-around mode.

14. The apparatus of claim 6 , wherein the cache comprises an array of non-volatile solid-state storage elements arranged in banks and accessed in parallel.

15. The apparatus of claim 6 , further comprising a direct memory access (“DMA”) controller that controls DMA operations.

16. The apparatus of claim 6 , further comprising a groomer module that recovers storage capacity of the cache in response to a storage capacity recovery event, wherein the storage capacity recovery event triggers the groomer module to recover storage capacity of the cache.

17. The apparatus of claim 6 , further comprising a write data pipeline having an error-correcting code (“ECC”) generator.

18. The apparatus of claim 6 , wherein the predetermined threshold is a maximum dirty write pool size.

19. A system comprising:

a processor;

a storage controller for a nonvolatile solid-state storage device, the nonvolatile solid-state storage device in communication with the processor over one or more communications buses;

a cache controller in communication with the storage controller, the cache controller configured to:

monitor storage requests received by the cache controller, the storage requests comprising read requests and write requests;

dynamically adjust a size of a read pool of the cache to increase a read hit rate of the storage requests, wherein determining the target read pool size comprises reducing the target read pool size in response to a read miss;

dynamically adjust a size of a dirty write pool of the cache to increase a dirty write hit rate of the storage requests;

adjust a destage rate for destaging dirty write data from the dirty write pool of the cache; and

set the destage rate so that the size of the dirty write pool is within a predetermined threshold.

Assignments (4)
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038812/0954 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2016
From: LONGITUDE ENTERPRISE FLASH SARL
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 038324/0628 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2016
From: INTELLIGENT INTELLECTUAL PROPERTY HOLDINGS 2 LLC
To: PS12 LUXCO S.A.R.L.
Reel/Frame 037516/0180 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2016
From: PS12 LUXCO S.A.R.L.
To: LONGITUDE ENTERPRISE FLASH S.A.R.L.
Reel/Frame 037516/0265 →