Co-support for XFD packaging
View Patent ↗A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements.
1. A microelectronic package, comprising:
a dielectric element having first and second oppositely facing surfaces, and having first and second spaced apart apertures each extending between the first and second surfaces, the dielectric element further having first and second parallel edges extending between the first and second surfaces, a first region of the second surface disposed between the first aperture and the first edge, a second region of the second surface being disposed between the second aperture and the second edge; and
first and second microelectronic elements each having a front face facing the first surface and a rear face facing away from the first surface, each microelectronic element having contacts exposed at the respective front face,
the dielectric element having terminals at the second surface, the contacts of the first microelectronic element overlying the first aperture and electrically coupled with the terminals, and the contacts of the second microelectronic element overlying the second aperture and electrically coupled with the terminals,
wherein the terminals include first terminals and second terminals, the second terminals including at least some second terminals configured to carry address information for specifying each individual addressable memory location within the memory storage arrays,
the second terminals including a first group thereof disposed in the first region adjacent the first edge of the second surface, and a second group thereof disposed in the second region adjacent the second edge of the second surface, the second terminals configured to carry all of the address information usable by circuitry within the microelectronic package.
2. The microelectronic package as claimed in claim 1 , wherein the second terminals in the first region are coupled with the contacts of the first microelectronic element and are not coupled with the contacts of the second microelectronic element, and the second terminals in the second region are coupled with the contacts of the second microelectronic element and are not coupled with the contacts of the first microelectronic element.
3. The microelectronic package as claimed in claim 1 , wherein the first group of second terminals and the second group of second terminals are each configured to carry all of the same signals.
4. The microelectronic package as claimed in claim 1 , wherein the signal assignments of the at least some second terminals in the first region are symmetric about a theoretical axis extending parallel to said first and second edges of said dielectric element with the signal assignments of the at least some second terminals in the second region.
5. The microelectronic package as claimed in claim 4 , wherein the axis is located within one ball pitch of the terminals of a centerline of the dielectric element located equidistant between the first and second opposed edges.
6. The microelectronic package as claimed in claim 4 , wherein the second terminals in each of the first and second regions include at least some second terminals having command information signal assignments, and the signal assignments of the at least some second terminals having command information signal assignments in the first region are symmetric about the axis with the signal assignments of the at least some second terminals having command information signal assignments in the second region.
7. The microelectronic package as claimed in claim 1 , wherein the second terminals of the first and second groups are disposed at positions within respective first and second grids, and columns of the second terminals in the first and second grids extend in a direction parallel to the first and second opposed edges of the dielectric element.
8. The microelectronic package as claimed in claim 1 , wherein the first terminals are disposed between the first and second apertures and are configured to carry data signals for read and write access to random access addressable memory locations of memory storage arrays within the microelectronic package.
9. The microelectronic package as claimed in claim 8 , wherein the first terminals are configured to carry all of the data signals for read and write access to the random access addressable memory locations of the memory storage arrays within the microelectronic package.
10. The microelectronic package as claimed in claim 8 , wherein each of the first terminals is coupled with a corresponding one of the contacts of the first microelectronic element and a corresponding one of the contacts of the second microelectronic element.
11. The microelectronic package as claimed in claim 8 , wherein the first terminals include a first group thereof disposed on a first side of a theoretical axis and a second group thereof disposed on a second side of the axis opposite from the first side, each of the first and second groups configured to carry the same data signals.
12. The microelectronic package as claimed in claim 11 , wherein the first group of the first terminals are coupled with the contacts of the first microelectronic element and are not coupled with the contacts of the second microelectronic element, and the second group of the first terminals are coupled with the contacts of the second microelectronic element and are not coupled with the contacts of the first microelectronic element.
13. The microelectronic package as claimed in claim 11 , wherein the axis is located within one ball pitch of the terminals of a centerline of the dielectric element located equidistant between the first and second opposed edges.
14. The microelectronic package as claimed in claim 8 , wherein the first terminals of the first group have modulo-X symmetry about the axis with the second group of the first terminals, X being a multiple of 8 and a whole number of at least one.
15. The microelectronic package as claimed in claim 1 , wherein the front face of the first microelectronic element confronts the first surface of the dielectric element, and wherein the front face of the second microelectronic element at least partially overlies the rear face of the first microelectronic element.
16. The microelectronic package as claimed in claim 1 , wherein the front face of all of the microelectronic elements are arranged in a single plane parallel to the first surface of the dielectric element.
17. The microelectronic package as claimed in claim 1 , further comprising leads extending through the apertures, the contacts being coupled with the terminals via the leads.
18. The microelectronic package as claimed in claim 1 , wherein the leads include first leads extending through the first aperture to the contacts of the first microelectronic element and second leads extending through the second aperture to the contacts of the second microelectronic element.
19. The microelectronic package as claimed in claim 17 , wherein the dielectric element includes bond pads exposed at the second surface and electrically coupled with the terminals, and the leads include wire bonds extending through the apertures from the contacts to the bond pads.
20. The microelectronic package as claimed in claim 1 , wherein the first and second apertures are elongated in a same direction, the same direction parallel to the edges of the dielectric element.
21. The microelectronic package as claimed in claim 1 , wherein the second terminals in each of the first and second regions include at least some second terminals having command information signal assignments, and the signal assignments of the at least some second terminals having command information signal assignments in the first region are symmetric about the theoretical axis with the signal assignments of the at least some second terminals having command information signal assignments in the second region.
22. A system comprising a microelectronic package according to claim 1 and one or more other electronic components electrically connected to the microelectronic package.
23. The system as claimed in claim 22 , further comprising a housing, the microelectronic package and the one or more other electronic components being assembled with the housing.