Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.
1. A method for fabricating semiconductor device, comprising:
providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask;
removing part of the first hard mask;
forming a second hard mask layer on the first hard mask and the ILD layer; and
planarizing part of the second hard mask layer and part of the ILD layer at the same time to form a second hard mask on the first hard mask.
2. The method of claim 1 , wherein the width of the second hard mask is greater than the width of the first hard mask.
3. The method of claim 1 , wherein a spacer and a contact etch stop layer (CESL) are formed adjacent to the gate structure and the first hard mask, the method further comprises:
removing part of the first hard mask and part of the spacer; and
forming the second hard mask on the first hard mask and the spacer.
4. The method of claim 1 , wherein a spacer and a contact etch stop layer (CESL) are formed adjacent to the gate structure and the first hard mask, the method further comprises:
removing part of the first hard mask, part of the spacer, and part of the CESL; and
forming the second hard mask on the first hard mask, the spacer, and the CESL.
5. The method of claim 1 , wherein the first hard mask and the second hard mask comprise different material.
6. The method of claim 1 , wherein the second hard mask comprises TiN.
7. The method of claim 1 , further comprising forming a cap layer on the first hard mask and the ILD layer before forming the second hard mask layer.
8. The method of claim 7 , wherein the cap layer comprises an oxide layer.
9. The method of claim 1 , further comprising removing part of the ILD layer after forming the second hard mask.
10. The method of claim 1 , further comprising using the second hard mask to form a contact hole adjacent to the gate structure after planarizing part of the second hard mask layer.
11. A method for fabricating semiconductor device, comprising:
providing a substrate having a gate structure thereon, a spacer around the gate structure, a contact etch stop layer (CESL) adjacent to the spacer, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask;
removing part of the first hard mask and part of the spacer simultaneously so that a top surface of the first hard mask and the spacer is lower than a top surface of the CESL;
forming a second hard mask layer on the first hard mask and the ILD layer; and
planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.
12. The method of claim 11 , wherein the top surfaces of the second hard mask and the CESL are coplanar.