Improving linearity in semiconductor devices
A field effect transistor that has a source, a drain, a gate and a semiconductor region. The semiconductor region has a source access region between the gate and the source, a drain access region between the gate and the drain, and a channel region under the gate. The channel region under the gate has a maximum current-carrying capability that is lower than a maximum current-carrying capability of the source access region.
1. A field effect transistor, comprising:
a source;
a drain;
a gate; and
a semiconductor region between the source and the drain, the semiconductor region having a source access region between the gate and the source, a drain access region between the gate and the drain, and a channel region under the gate that includes a two-dimensional electron gas extending across an entire length of the gate, wherein the channel region under the gate has a maximum current-carrying capability that is lower than a maximum current-carrying capability of the source access region.
2. The field effect transistor of claim 1 , wherein the channel region under the gate has a smaller width than that of the source access region.
3. The field effect transistor of claim 1 , wherein the channel region under the gate has a smaller current carrying cross-sectional area than that of the source access region.
4. The field effect transistor of claim 1 , wherein the field effect transistor comprises a plurality of channel regions under the gate.
5. The field effect transistor of claim 4 , wherein the plurality of channel regions under the gate includes nanowires of semiconductor material.
6. The field effect transistor of claim 5 , wherein the nanowires do not extend beyond an area covered by the gate.
7. The field effect transistor of claim 1 , further comprising at least one region of limited conductivity under the gate, between the source access region and the drain access region, the at least one region of limited conductivity having a lower conductivity that that of the channel region under the gate.
8. The field effect transistor of claim 7 , wherein the at least one region of limited conductivity comprises at least one insulating region.
9. The field effect transistor of claim 1 , wherein the semiconductor region comprises a nitride semiconductor material.
10. The field effect transistor of claim 9 , wherein the nitride semiconductor material comprises a gallium nitride semiconductor material.
11. The field effect transistor of claim 1 , wherein the source access region comprises a plurality of channels at different depths and the channel region under the gate has a smaller quantity of channels than a quantity of the plurality of channels.
12. The field effect transistor of claim 1 , wherein the channel region under the gate has an amount of current-carrying semiconductor material that is lower than an amount of current-carrying semiconductor material of the source access region.
13. The field effect transistor of claim 1 , wherein a source-drain current of the field effect transistor is not limited by the current-carrying capability of the source access region or the drain access region.
14. The field effect transistor of claim 1 , wherein the channel region under the gate has a lower conductivity than that of the source access region.
15. The field effect transistor of claim 1 , further comprising a doped region over the source access region and the drain access region and not over the channel region under the gate.
16. The field effect transistor of claim 1 , wherein a semiconductor material under the gate is different from a material of the source access region or drain access region.
17. A field effect transistor, comprising:
a first electrode;
a second electrode;
a gate having a gate length;
a first channel region covered by the gate and extending across the gate length; and
a second channel region not covered by the gate, positioned between the first electrode and the gate,
wherein the first channel region has a first cross-section perpendicular to a line between the first electrode and the second electrode,
wherein the second channel region has a second cross-section perpendicular to the line between the first electrode and the second electrode,
wherein an area of the first cross-section of the first channel region is smaller than an area of the second cross-section of the second channel region, and
wherein the second channel region is wider than the first channel region in a width direction perpendicular to the line between the first electrode and the second electrode.
18. The field effect transistor of claim 17 , wherein the first channel region comprises a nitride semiconductor material.
19. The field effect transistor of claim 18 , wherein the nitride semiconductor material comprises a gallium nitride semiconductor material.
20. The field effect transistor of claim 17 , wherein the first channel region comprises at least one nanowire.
21. The field effect transistor of claim 20 , wherein the first channel region comprises a plurality of nanowires.
22. The field effect transistor of claim 20 , wherein the at least one nanowire comprises a first nanowire having a fin-like shape.
23. The field effect transistor of claim 17 , further comprising at least one insulating region under the gate.
24. The field effect transistor of claim 23 , wherein the at least one insulating region comprises a region of damaged semiconductor material.
25. The field effect transistor of claim 17 , wherein the first channel region includes a two-dimensional electron gas extending across the gate length.