IP Library Granted Patent US 9,940,270
Granted Patent B2
US 9,940,270 · App. 14/838,601 · Granted Apr 10, 2018

Multiple request notification network for global ordering in a coherent mesh interconnect

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Quick Facts
Patent No.
US 9,940,270
App. No.
14/838,601
Granted
Apr 10, 2018
Kind
B2
Abstract

A data processing system includes a plurality of processing unit. Each processing unit includes notification storage circuitry configured to store a notification indicator corresponding to each processing unit which indicates whether the processing unit has an outstanding coherent memory request, and multiple request storage circuitry configured to store a multiple request indicator corresponding to each processing unit which indicates whether the processing unit has more than one outstanding request. The data processing system also includes an interconnect network coupled between the processing units and configured to broadcast coherent memory requests from a requesting processing unit of the plurality of processing units to other processing units of the plurality of processing units.

Claims (35)

1. A data processing system, comprising:

a plurality of processing units, each processing unit comprising:

notification storage circuitry configured to store a notification indicator corresponding to each processing unit which indicates whether the processing unit has an outstanding coherent memory request;

multiple request storage circuitry configured to store a multiple request indicator corresponding to each processing unit which indicates whether the processing unit has more than one outstanding request;

control logic configured to select a priority processing unit having multiple outstanding requests based on the multiple request indicators in the multiple request storage circuitry; and

multiple request count storage circuitry configured to store a count of outstanding requests corresponding to the priority processing unit;

an interconnect network coupled between the processing units and configured to broadcast coherent memory requests from a requesting processing unit of the plurality of processing units to other processing units of the plurality of processing units,

a notification network coupled between the processing units and configured to communicate the notification indicator between the processing units;

a multiple request network coupled between the processing units and configured to communicate the multiple request indicator between the processing units; and

a multiple request count network coupled between the processing units and configured to communicate the count between the processing units.

2. The data processing system of claim 1 , wherein control circuitry within each processing unit is configured to perform a bit-wise OR of received notification indicators corresponding to a same processing unit of the plurality of processing units and, in response to the bit-wise OR, update the notification storage circuitry.

3. The data processing system of claim 2 , wherein control circuitry within each processing unit is configured to perform a bit-wise OR of received multiple request indicators corresponding to a same processing unit of the plurality of processing units and, in response to the bit-wise OR, update the multiple request storage circuitry.

4. The data processing system of claim 1 , wherein each notification indicator is a single bit and each multiple request indicator is a single bit.

5. The data processing system of claim 1 , the control logic of each processing unit configured to determine an ordering of requests based on the notification indicators in the notification storage circuitry and, if any processing unit has more than one outstanding request, based on the selected priority processing unit and count stored in the multiple request count circuitry.

6. In a data processing system having a plurality of processing units, wherein the plurality of processing units are interconnected with a notification network, a multiple request network, and a multiple request count network, a method comprising:

setting a notification indicator in notification storage circuitry within each processing unit of the plurality of processing units having one or more outstanding memory coherency requests;

setting a multiple request indicator in multiple request storage circuitry within each processing unit of the plurality of processing units having two or more outstanding memory coherency requests;

within each processing unit, using the multiple request indicators set within the multiple storage circuitry to determine a priority processing unit among processing units having two or more outstanding memory coherency requests;

storing within each processing unit a count of a number of outstanding memory coherency requests of the priority processing unit;

determining, by the priority processing unit, the count of the number of outstanding memory coherency requests and providing the count to the multiple request count network

providing the notification indicator set within each processing unit to the notification network; and

providing the multiple request indicator set within each processing unit to the multiple request network.

7. The method of claim 6 , wherein the setting the notification indicator and the setting the multiple request indicator occurs within a predetermined notification window.

8. The method of claim 7 , wherein the predetermined notification window provides sufficient time for the set notification indicators to propagate to all processing units of the plurality of processing units by way of the notification network.

9. The method of claim 8 , wherein the determining the priority processing unit is performed within each processing unit after expiration of the predetermined notification window.

10. The method of claim 6 , further comprising: within each processing unit, using a same algorithm which uses the notification indicators set within the notification storage circuitry, the determined priority processing unit, and the count provided to the multiple request count network to determine a global ordering of the coherent memory requests from the plurality of processing units.

11. A data processing system comprising a plurality of processing units interconnected by a notification network, a multiple request network, and a multiple request count network, each processing unit comprising:

notification storage circuitry configured to store a notification indicator corresponding to each processing unit which indicates whether the processing unit has an outstanding coherent memory request;

multiple request storage circuitry configured to store a multiple request indicator corresponding to each processing unit which indicates whether the processing unit has more than one outstanding request;

multiple request count circuitry configured to store a count of outstanding requests corresponding to a priority processing unit; and

control logic configured to select the priority processing unit from the plurality of processing units having multiple outstanding requests based on the multiple request indicators in the multiple request storage circuitry, wherein the control logic in each processing unit is further configured to:

provide the notification indicator to the notification network,

provide the multiple request indicator to the multiple request network, and

if the processing unit is the priority processing unit, determine the count of outstanding requests and provide the count to the multiple request count network.

12. The data processing unit of claim 11 , wherein the control logic in each processing unit is further configured to apply a same algorithm to determine an ordering of requests based on the notification indicators in the notification storage circuitry, the priority processing unit, and the count of outstanding requests.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2021
From: NXP B.V.
To: FUTURE LINK SYSTEMS, LLC
Reel/Frame 055115/0491 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2015
From: MORALES, FERNANDO A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 036446/0130 →