Receiving device
According to one embodiment, a receiving device includes a first PLL circuit, a second PLL circuit, and a control circuit. The first PLL circuit includes a first VCO and extracts a first clock from a received first packet. The second PLL circuit includes a second VCO and outputs a second clock acquired by multiplying the received clock by N. The control circuit applies a control signal of the second VCO to a first line controlling the first VCO during a first time from start of reception of the first packet.
1. A receiving device comprising:
a first PLL circuit that includes a first VCO and extracts a first clock from a received first packet;
a second PLL circuit that includes a second VCO and outputs a second clock acquired by multiplying a received clock by N, the received clock having a frequency of 1/N of a bit rate of the first packet, N being a natural number; and
a control circuit that includes a first circuit and a second circuit, the first circuit applying a control signal of the second VCO to a first line during a first time from start of reception of the first packet, the first line controlling the first VCO, the second circuit causing the first PLL circuit to be in a standby state during a non-reception period of the first packet.
2. The receiving device according to claim 1 , wherein the second circuit starts the first PLL circuit to operate at start time of the reception of the first packet.
3. The receiving device according to claim 1 , wherein the second circuit causes the second PLL circuit to be in a standby state during a period from a timing at which synchronization of the first PLL circuit is established to end of the reception of the first packet.
4. The receiving device according to claim 1 , wherein
before the first PLL circuit receives the first packet, the second PLL circuit receives the clock.
5. The receiving device according to claim 1 , a frequency of the first clock and a frequency of the second clock are the same.
6. The receiving device according to claim 1 , wherein, when the first PLL circuit is in the standby state, a part of the first PLL circuit is in an operable state and the other of the first PLL circuit is in an operation stopped state.
7. The receiving device according to claim 6 , wherein the operation stopped state is a state having power consumption lower than that of a normal state.
8. The receiving device according to claim 1 , the first time is set based on the a lockup time of the first PLL circuit.
9. The receiving device according to claim 1 , the control circuit is operated during the operation of the receiving device.
10. The receiving device according to claim 1 , the control signal of the second VCO is a control voltage of the second VCO.
11. The receiving device according to claim 1 , wherein
the first PLL circuit comprises:
a first phase comparator that performs a phase comparison between the first packet and the first clock output from the first VCO;
a first charge pump that generates a current corresponding to a phase difference acquired by the first phase comparator;
a first loop filter that converts the current generated by the first charge pump into a first control voltage;
the first VCO that generates the first clock having a frequency corresponding to the first control voltage, and
wherein the first line is a connection line between an output of the first charge pump and an input of the first loop filter or a connection line between an output of the first loop filter and an input of the first VCO.
12. The receiving device according to claim 11 , wherein, when the first PLL circuit is in the standby state, the first phase comparator is in an operable state, and the first charge pump, the first loop filter, the first VCO are in an operation stopped state.
13. The receiving device according to claim 11 , wherein
the second circuit causes the first PLL circuit to be in the standby state during the non-reception period of the first packet based on a state signal input from the first phase comparator.
14. The receiving device according to claim 13 , wherein the state signal becomes on during a reception period of the first packet, and becomes off during the non-reception period of the first packet.
15. The receiving device according to claim 1 , wherein
the second PLL circuit comprises:
a frequency comparator that performs a frequency comparison between the received clock and a feedback clock;
a second charge pump that generates a current corresponding to a frequency difference acquired by the frequency comparator;
a second loop filter that converts the current generated by the second charge pump into a second control voltage;
the second VCO that generates the second clock having a frequency corresponding to the second control voltage; and
a frequency divider that divides the second clock output from the second VCO into a frequency of 1/N and outputs the feedback clock.
16. A receiving device comprising:
a first PLL circuit that includes a first VCO and extracts a first clock from a received first packet;
a second PLL circuit that includes a second VCO and outputs a second clock acquired by multiplying a received clock by N, the received clock having a frequency of 1/N of a bit rate of the first packet, N being a natural number; and
a control circuit that includes a first circuit, the first circuit applying, to a first line, a first converted signal acquired by converting a control signal of the second VCO based on voltage-to-frequency characteristics of the first and second VCOs during a first time from start of reception of the first packet, the first line controlling the first VCO.