Delay locked loop (DLL) locked to a programmable phase
An asynchronous digital logic is used to provide a pulse. A pulse train is filtered to determine an analog measurement based at least in part on the duty cycle of the pulse. The analog measurement is compared with a tunable reference associated with a programmable locked delay for the DLL. A digital code is sequenced based at least in part on the comparison. A digitally controlled delay line is programmed based at least in part on the digital code.
1. A system for a digital delay locked loop (“DLL”), comprising:
an asynchronous digital logic;
an analog filter coupled to an output of the asynchronous digital logic;
an analog comparator coupled to: (1) an output of the analog low pass filter; and (2) a tunable reference associated with a programmable locked delay for the DLL;
a synchronous digital logic coupled to an output of the analog comparator; and
a digitally controlled delay line coupled to an output of the synchronous digital logic, wherein the asynchronous digital logic is coupled to a reference clock and an output of the digitally controlled delay line.
2. The system as recited in claim 1 , further comprising a common digital power supply providing common supply voltage for the:
asynchronous digital logic; and
analog comparator.
3. The system as recited in claim 2 , wherein the common digital power supply further provides common supply voltage for the synchronous digital logic.
4. The system as recited in claim 1 , wherein the asynchronous digital logic is an exclusive OR (“XOR”) logic.
5. The system as recited in claim 4 , wherein the XOR logic operates above twice the reference clock.
6. The system as recited in claim 1 , wherein the programmable locked delay for the DLL may be set between 0 and 180 degrees.
7. The system as recited in claim 1 , wherein the digitally controlled delay line comprises an analog delay line coupled with a digital-to-analog converter (DAC).
8. The system as recited in claim 1 , wherein the digitally controlled delay line is a master delay line, and the DLL further comprises a slave delay line coupled with the master delay line.
9. The system as recited in claim 8 , wherein the master delay line uses a same number of delay cells as the slave delay line.
10. The system as recited in claim 8 , wherein the master delay line is a replica of the slave delay line.
11. The system as recited in claim 8 , wherein the slave delay line is a significant distance from a global DLL on a chip floorplan.
12. The system as recited in claim 1 , wherein the analog filter is a passive low-pass filter.
13. The system as recited in claim 12 , wherein the passive low-pass filter is a passive first-order low-pass filter.
14. The system as recited in claim 1 , wherein the tunable reference is based at least in part by a register DAC.
15. The system as recited in claim 1 , wherein the synchronous digital logic is an up/down counter.
16. The system as recited in claim 15 , wherein the up/down counter is coupled to the digitally controlled delay line by a digital code.
17. The system as recited in claim 1 , wherein the synchronous digital logic is clocked at a sub-sampling rate based at least in part on a loop settling time.
18. The system as recited in claim 1 , wherein the synchronous digital logic is further configured to receive a power-saving register value when the DLL is powered-down.
19. A method for a DLL, comprising:
using an asynchronous digital logic to provide a pulse;
filtering the pulse train to determine an analog measurement based at least in part on the duty cycle of the pulse;
comparing the analog measurement with a tunable reference associated with a programmable locked delay for the DLL;
sequencing to a digital code based at least in part on the comparison; and
programming a digitally controlled delay line based at least in part on the digital code, wherein the asynchronous digital logic is coupled to a reference clock and an output of the digitally controlled delay line.