Sizing a cache while taking into account a total bytes written requirement

1. A system, comprising:

solid state storage including a cache and being configured to operate in a variable size mode in which the cache is permitted to vary in size and a fixed size mode in which the size of the cache has a fixed size; and

a solid state storage controller configured to:

obtain a total bytes written (TBW) requirement associated with the solid state storage;

determine the size of the cache based at least in part on the TBW requirement and a remaining program and erase (P/E) count;

adjust the size of the cache to be the determined size when the P/E count is less than a maximum count; and

transition the solid state storage to the fixed size mode, adjusting the size of the cache to the fixed size, when the remaining P/E count is greater than or equal to the maximum count.

2. The system of claim 1 , wherein the solid state storage controller includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

3. The system of claim 1 , wherein the cache includes a plurality of single-level cells (SLC) and a regular drive portion of the solid state storage includes one or more of the following: a plurality of multi-level cells (MLC) or a plurality of tri-level cells (TLC).

4. The system of claim 1 , wherein the solid state storage controller is further configured to:

determine if one or more fixed size mode criteria have been met;

in the event the fixed size mode criteria have been met:

obtain a fixed size; and

adjust the size of the cache to be the fixed size; and

in the event the fixed size mode criteria have not been met, perform the steps of obtaining, determining, and adjusting.

5. The system of claim 1 , wherein the solid state storage controller is configured to determine the size of the cache, including by:

determining a plurality of combinations of (1) cache size and (2) remaining (P/E) count in the variable size mode which do not violate the TBW requirement; and

selecting one of the plurality of combinations, wherein a cache size corresponding to the selected combination is the determined cache size and a remaining P/E count corresponding to the selected combination is associated with the end of the variable size mode.

6. The system of claim 5 , wherein the determination of the plurality of combinations is based at least in part on a future state of the solid state storage during a fixed size mode which follows the variable size mode.

7. The system of claim 1 , wherein:

the size of the cache is being downsized; and

the solid state storage controller is configured to downsize the cache, including by:

determining if a size reallocation flag is set; and

in the event it is determined that the size reallocation flag is not set:

setting the size reallocation flag; and

designating one or more empty cache blocks as empty regular drive blocks.

8. The system of claim 7 , wherein the solid state storage controller is further configured to:

perform a garbage collection process on the cache, wherein valid data in ingested cache blocks is output to the regular drive; and

open a regular drive block for the garbage collection process using an empty regular drive block from the cache downsizing process.

9. The system of claim 1 , wherein the solid state storage controller is further configured to:

determine if the cache has a higher average program and erase (P/E) count than the regular drive;

in the event it is determined that the cache has a higher average P/E count, exchange one or more free cache blocks with the highest P/E count(s) with one or more free regular drive blocks with the lowest P/E count(s); and

in the event it is determined that the regular drive has a higher average P/E count, exchange one or more free cache blocks with the lowest P/E count(s) with one or more free regular drive blocks with the highest P/E count(s).

10. A method, comprising:

obtaining a total bytes written (TBW) requirement associated with solid state storage that includes a cache and is configured to operate in a variable size mode in which the cache is permitted to vary in size and a fixed size mode in which the size of the cache has a fixed size;

determining the size of the cache based at least in part on the TBW requirement and a remaining program and erase (P/E) count;

adjusting the size of the cache to be the determined size when the P/E count is less than a maximum count; and

transitioning the solid state storage to the fixed size mode, adjusting the size of the cache to the fixed size, when the remaining P/E count is greater than or equal to the maximum count.

11. The method of claim 10 , wherein the method is performed by a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

12. The method of claim 10 , wherein the cache includes a plurality of single-level cells (SLC) and a regular drive portion of the solid state storage includes one or more of the following: a plurality of multi-level cells (MLC) or a plurality of tri-level cells (TLC).

13. The method of claim 10 further comprising:

determining if one or more fixed size mode criteria have been met;

in the event the fixed size mode criteria have been met:

obtaining a fixed size; and

adjusting the size of the cache to be the fixed size; and

in the event the fixed size mode criteria have not been met, perform the steps of obtaining, determining, and adjusting.

14. The method of claim 10 , wherein determining the size of the cache includes:

determining a plurality of combinations of (1) cache size and (2) remaining (P/E) count in the variable size mode which do not violate the TBW requirement; and

selecting one of the plurality of combinations, wherein a cache size corresponding to the selected combination is the determined cache size and a remaining P/E count corresponding to the selected combination is associated with the end of the variable size mode.

15. The method of claim 14 , wherein determining the plurality of combinations is based at least in part on a future state of the solid state storage during a fixed size mode which follows the variable size mode.

16. The method of claim 10 , wherein:

the size of the cache is being downsized; and

downsizing the cache includes:

determining if a size reallocation flag is set; and

in the event it is determined that the size reallocation flag is not set:

setting the size reallocation flag; and

designating one or more empty cache blocks as empty regular drive blocks.

17. The method of claim 16 further comprising:

performing a garbage collection process on the cache, wherein valid data in ingested cache blocks is output to the regular drive; and

opening a regular drive block for the garbage collection process using an empty regular drive block from the cache downsizing process.

18. The method of claim 10 further comprising:

determining if the cache has a higher average program and erase (P/E) count than the regular drive;

in the event it is determined that the cache has a higher average P/E count, exchanging one or more free cache blocks with the highest P/E count(s) with one or more free regular drive blocks with the lowest P/E count(s); and

in the event it is determined that the regular drive has a higher average P/E count, exchanging one or more free cache blocks with the lowest P/E count(s) with one or more free regular drive blocks with the highest P/E count(s).

19. A computer program product, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:

obtaining a total bytes written (TBW) requirement associated with solid state storage that includes a cache and is configured to operate in a variable size mode in which the cache is permitted to vary in size and a fixed size mode in which the size of the cache has a fixed size;

determining the size of the cache associated with the solid state storage based at least in part on the TBW requirement and a remaining program and erase (P/E) count;

adjusting the size of the cache to be the determined size when the P/E count is less than a maximum count; and

transitioning the solid state storage to the fixed size mode, adjusting the size of the cache to the fixed size, when the remaining P/E count is greater than or equal to the maximum count.

20. The computer program product of claim 19 , wherein determining the size of the cache includes:

determining a plurality of combinations of (1) cache size and (2) remaining (P/E) count in the variable size mode which do not violate the TBW requirement; and

selecting one of the plurality of combinations, wherein a cache size corresponding to the selected combination is the determined cache size and a remaining P/E count corresponding to the selected combination is associated with the end of the variable size mode.