Routing Standard Cell-Based Integrated Circuits
This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.
1 . A semiconductor device comprising a semiconductor die, wherein the semiconductor die further comprises:
a bypass connection in a non-routing layer of the semiconductor die, wherein the bypass connection electrically couples a first bypass connector to a second bypass connector;
a first signal connection that connects the first bypass connector to a first transistor on the semiconductor die; and
a second signal connection that connects the second bypass connector to a second transistor on the semiconductor die.
2 . The semiconductor device of claim 1 wherein the first bypass connector and the second bypass connector are in a routing layer of the semiconductor die.
3 . The semiconductor device of claim 2 wherein the routing layer is a metal 1 routing layer and the non-routing layer is selected from the group consisting of a polysilicon layer and a diffusion layer.
4 . The semiconductor device of claim 1 wherein the bypass connection traverses underneath a power rail located in the routing layer of the semiconductor die.
5 . The semiconductor device of claim 4 wherein the first transistor is located on a different side of the power rail relative to the second transistor.
6 . The semiconductor device of claim 1 wherein the bypass connection corresponds to a functional standard cell selected from the group consisting of a NAND cell, a NOR cell, a latch cell, an inverter cell, an AND cell, and an OR cell.
7 . The semiconductor device of claim 1 wherein the functional standard cell is inserted during a place and route stage of an automated standard cell design flow to create the semiconductor die.
8 . An integrated circuit made by a method comprising:
locating a routing congestion area in response to performing a first route of a plurality of standard cells corresponding to the integrated circuit on a design floorplan, wherein the routing congestion area has an amount of routing violations on the design floorplan that exceed a pre-defined threshold;
inserting a multi-height routing cell on the design floorplan in response to locating the routing congestion area, wherein the multi-height routing cell comprises a bypass connection corresponding to a non-routing layer of the integrated circuit that couples a first bypass connector to a second bypass connector;
connecting the multi-height routing cell to a first one and second one of the plurality of standard cells, the connecting resulting in the first standard cell coupled to the second standard cell through the multi-height routing cell and a reduction in the amount of routing violations; and
generating mask layer data that incorporates the multi-height routing cell, wherein the mask layer data is configured to generate a plurality of masks for construction of the integrated circuit.
9 . The integrated circuit of claim 8 wherein the routing congestion area comprises one or more power rails and one or more signal routes from the first route, and wherein the method further comprises:
removing the one or more power rails and the one or more signal routes from the routing congestion area;
performing a second route using routing constraints that allow insertion of a temporary routing segment across a prior location of one of the one or more removed power rails; and
replacing the temporary routing segment with the multi-height routing cell.
10 . The integrated circuit of claim 9 wherein the method further comprises:
adding one or more new power rails to the design floorplan subsequent to the insertion of the multi-height routing cell, wherein a selected one of the new power rails couples to a power rail segment in the multi-height routing cell, and wherein the bypass connection traverses underneath the power rail segment.
11 . The integrated circuit of claim 8 wherein the first bypass connector and the second bypass connector are in the multi-height routing cell and correspond to a routing layer of the integrated circuit.
12 . The integrated circuit of claim 11 wherein the routing layer corresponds to a metal 1 layer of the integrated circuit and the non-routing layer is selected from the group consisting of a polysilicon layer and a diffusion layer corresponding to the integrated circuit.
13 . The integrated circuit of claim 8 wherein the bypass connection is in a functional standard cell selected from the group consisting of a NAND cell, a NOR cell, a latch cell, an inverter cell, an AND cell, and an OR cell.
14 . The integrated circuit of claim 8 wherein the multi-height routing cell comprises a signal buffer coupled to the bypass connection.
15 . The integrated circuit of claim 8 wherein the multi-height routing cell comprises more than two metal layers corresponding to the integrated circuit.
16 . The integrated circuit of claim 8 wherein the multi-height routing cell comprises a metal routing segment corresponding to a routing layer that couples the bypass connection to the first bypass connector.
17 . The integrated circuit of claim 8 wherein the multi-height routing cell is inserted during a place and route stage of an automated standard cell design flow.