Buried low-resistance metal word lines for cross-point variable-resistance material memories
Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
1. A process comprising:
forming a first recess by use of a hard mask, in an upper semiconductive substrate that is disposed above a lower semiconductive substrate;
forming a spacer in the first recess;
forming a second recess that at least penetrates into the upper semiconductive substrate, and that forms a pillar in the upper semiconductive substrate;
forming a buried salicide word line in the pillar;
forming a shallow trench isolation adjacent the pillar;
forming a diode in a recess of the hard mask that exposes the pillar at an upper surface thereof; and
forming a variable-resistance material memory that is coupled to the diode.
2. The process of claim 1 , wherein forming the buried salicide word line in the pillar includes:
forming a metal over the pillar and in the second recess; and
heating the metal to form the buried salicide in the pillar.
3. The process of claim 1 , wherein forming the diode in the recess of the hard mask that exposes the pillar at the upper surface thereof includes:
etching the hard mask to form the recess in the hard mask;
forming an epitaxial first film above and on the pillar at the upper surface; and
forming an epitaxial second film above and on the epitaxial first film.
4. The process of claim 3 , wherein forming the variable-resistance material memory that is coupled to the diode includes:
siliciding a portion of the epitaxial second film to form a silicide contact;
forming a bottom electrode on the silicide contact;
forming the variable-resistance material memory on the bottom electrode; and
forming a top electrode on the variable-resistance material memory.
5. The process of claim 1 , wherein forming the diode in the recess of the hard mask that exposes the pillar at the upper surface thereof includes:
etching the hard mask to form the recess in the hard mask;
forming an epitaxial first film above and on the pillar at the upper surface; and
forming a second film above and on the epitaxial first film.
6. The process of claim 5 , wherein forming the variable-resistance material memory that is coupled to the diode includes:
siliciding a portion of the second film to form a silicide contact;
forming a bottom electrode on the silicide contact;
forming the variable-resistance material memory on the bottom electrode; and
forming a top electrode on the variable-resistance material memory.
7. The process of claim 1 , wherein the spacer is a first spacer and the process further including:
forming a second spacer in the second recess and on the first spacer;
etching below the second spacer to form an undercut below the pillar; and
filling the undercut with a buried oxide.
8. The process of claim 1 , wherein the variable-resistance material memory is selected from an alloy, a quasi-metal composition, a metal oxide, and a chalcogenide.
9. The process of claim 1 , wherein the variable-resistance material memory includes a phase-change material.
10. The process of claim 1 , wherein a silicide contact is formed in direct contact with the diode.
11. The process of claim 1 , wherein the buried salicide word line includes cobalt silicide.