Multi-level phase change device
View Patent ↗Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.
1. A memory cell device, comprising:
a top surface with a top electrode attached to the top surface;
a bottom surface with a bottom electrode attached to the bottom surface; and
a cell body between the top surface and the bottom surface, wherein the cell body comprises at least two alloys of a phase change material and a diffusion barrier, wherein the at least two alloys have different glass transition temperatures, wherein the at least two alloys are separated by the diffusion barrier, and wherein the at least two alloys comprise the same phase change material and are of different volumes.
2. The memory cell device of claim 1 , wherein the phase change material comprises any of selenium tellurium (SeTe), silicon tellurium (SiTe), antimony selenide (SbSe), tin selenide (SnSe), tin tellurium (SnTe), tin antimony (SnSb), germanium antimony (GeSb), germanium tellurium (GeTe), and silicon antimony (SiSb).
3. The memory cell device of claim 1 , wherein a glass transition temperature for a first alloy of the at least two alloys is at least 50 degrees Celsius greater but not more than 200 degrees greater than a glass transition temperature for a second alloy of the at least two alloys.
4. The memory cell device of claim 1 , wherein the two alloys have different levels of thickness.
5. The memory cell device of claim 1 , wherein the diffusion barrier has a resistivity less than 0.01 Ohm-cm.
6. The memory cell device of claim 1 , wherein the top electrode and the bottom electrode do not chemically interact with the cell body.
7. A system, comprising:
a storage device comprising a plurality of memory cells; and
a selector to access each of the plurality of memory cells in the storage device, wherein each of the memory cells comprises:
a top surface with a top electrode attached to the top surface;
a bottom surface with a bottom electrode attached to the bottom surface; and
a cell body between the top surface and the bottom surface, wherein the cell body comprises at least two alloys of a phase change material and a diffusion barrier, wherein the at least two alloys have different glass transition temperatures, wherein the at least two alloys are separated by the diffusion barrier, and wherein the at least two alloys comprise different alloys of the same phase change material and are of different volumes.
8. The system of claim 7 , wherein the phase change material comprises any of selenium tellurium (SeTe), silicon tellurium (SiTe), antimony selenide (SbSe), tin selenide (SnSe), tin tellurium (SnTe), tin antimony (SnSb), germanium antimony (GeSb), germanium tellurium (GeTe), and silicon antimony (SiSb).
9. The system of claim 7 , wherein the diffusion barrier has a resistivity less than 0.01 Ohm cm.
10. The system of claim 7 , wherein a glass transition temperature for a first alloy of the at least two alloys is at least 50 degrees Celsius greater but not more than 200 degrees greater than a glass transition temperature for a second alloy of the at least two alloys.
11. The system of claim 7 , wherein the two alloys have different levels of thickness.
12. The system of claim 7 , wherein, for each memory cell, the top electrode and the bottom electrode do not chemically interact with the cell body.