Patent Assignment
Reel/Frame 067982/0032
Change of Name
Recorded: 2024-06-27
Pages: 87
Assignor
SANDISK TECHNOLOGIES, INC.
Executed: 2024-06-21
Assignee
SANDISK TECHNOLOGIES, INC.
951 SANDISK DRIVE, LEGAL DEP., MILPITAS, CALIFORNIA, 95035
Covered Properties
(3136)
Mram Array and Access Method Thereof
Providing Streaming Media Data
Network Storage Virtualization Method and System
Error Correcting Memory Access Means and Method
Magnetic Memory and Method for Optimizing Write Current in a Magnetic Memory
Method of Efficient Data Management with Flash Storage System
Heat Assisted Switching in an Mram Cell Utilizing the Antiferromagnetic to Ferromagnetic Transition in Ferh
System and Method for Destructive Purge of Memory Device
Scr Matrix Storage Device
Magnetic Memory Device
Systems and Methods for a Mass Data Storage System Having a File-Based Interface to a Host and a Non-File-Based Interface to Secondary Storage
Registered Dual in-Line Memory Module Having an Extended Register Feature Set
System and Method for Destructive Purge of Memory Device
System and Method for Detecting and Reducing Data Corruption in a Storage Device
Parallel Data Storage System
Memory Array Having Memory Cells Formed from Metallic Material
Data Storage Device, and Method for Rewriting Data in Nonvolatile Memory
Systems and Methods for Measuring the Useful Life of Solid-State Storage Devices
System and Method for Managing Security of a Memory Device
System for Controlling Use of a Solid-State Storage Subsystem
Patent:
7,765,373 →
Application:
11/475,386 →
Systems and Methods for Storing Data in Segments of a Storage Subsystem
Patent:
7,447,807 →
Application:
11/480,276 →
Systems and Methods for Segmenting and Protecting a Storage Subsystem
Patent:
7,509,441 →
Application:
11/480,303 →
Method and System for Secure Data Storage
Magnetic Random Access Memory (Mram) Having Increased Reference Layer Anisotropy Through Ion Beam Etch of Magnetic Layers
Low-Voltage, Low-Power-Consumption, and High-Speed Differential Current-Sense Amplification
Enhanced Data Access in a Storage Device
Device Recoverable Purge for Flash Storage Device
Methods and Apparatus for Performing Resilient Firmware Upgrades to a Functioning Memory
End Point Detection for Direct Ion Milling to Induce Magnetic Anisotropy in a Magnetic Layer
Magnetic Medium Having a Soft Underlayer with a Magnetic Anisotropy
High Density Spin Torque Three Dimensional (3D) Memory Arrays Addressed with Microwave Current
Storage Subsystem with Configurable Buffer
Solid State Storage Subsystem for Embedded Applications
Solid State Storage Subsystem for Embedded Applications
Techniques for Implementing Virtual Storage Devices
Method for Delineation of Phase Change Memory (Pcm) Cells Separated by Pcm and Upper Electrode Regions Modified to Have High Film Resistivity
Current-Perpendicular-To-The-Plane (Cpp) Magnetoresistive Sensor with Cofege Ferromagnetic Layers
Multi-Interface and Multi-Bus Structured Solid-State Storage Subsystem
Increased Anisotropy Induced by Direct Ion Etch for Telecommunications/Electronics Devices
Systems and Apparatus for Main Memory with Non-Volatile Type Memory Modules, and Related Technologies
Methods for Main Memory with Non-Volatile Type Memory Modules, and Related Technologies
Storage Subsystem Capable of Adjusting Ecc Settings Based on Monitored Conditions
Methods and Apparatus of Dual Inline Memory Modules for Flash Memory
Non-Linear Conductor Memory
Asymmetric Memory Migration in Hybrid Main Memory
Three-Dimensional Magnetic Memory with Multi-Layer Data Storage Layers
Distributed Addressing in Solid-State Storage
Parallel Data Transfer in Solid-State Storage
Multi-Channel Solid-State Storage System
Tree-Structure Memory Device
Solid State Storage Subsystem That Maintains and Provides Access to Data Reflective of a Failure Risk
Interface for Enabling a Host Computer to Retrieve Device Monitor Data from a Solid State Storage Subsystem
Parallel Data Storage System
Storage Subsystem with Embedded Circuit for Protecting Against Anomalies in Power Signal from Host
Patent:
7,733,712 →
Application:
12/123,932 →
Flash Memory Allocation for Improved Performance and Endurance
Single Sector Write Operation in Flash Memory
Read/Write Elements for a Three-Dimensional Magnetic Memory
Method and Apparatus for Write Enable and Inhibit for High Density Spin Torque Three Dimensional (3D) Memory Arrays
Enhanced Erase for Flash Storage Device
Architecture for Optimizing Execution of Storage Access Commands
Patent:
8,825,940 →
Application:
12/326,780 →
Distributing Metadata Across Multiple Different Disruption Regions Within an Asymmetric Memory System
Prioritized Erasure of Data Blocks in a Flash Storage Device
Staged-Backup Flash Backed Dram Module
State of Health Monitored Flash Backed Dram Module
Flash Backed Dram Module Storing Parameter Information of the Dram Module in the Flash
Flash Backed Dram Module with State of Health and/or Status Information Accessible Through a Configuration Data Bus
Flash Backed Dram Module with a Selectable Number of Flash Chips
Memory Modules for Two-Dimensional Main Memory
Systems for two-dimensional main memory including memory modules with read-writeable non-volatile memory devices
Methods for Upgrading Main Memory in Computer Systems to Two-Dimemsional Memory Modules and Master Memory Controllers
Redundant Purge for Flash Storage Device
Verified Purge for Flash Storage Device
Diagonal Connection Storage Array
Systems and Methods for Reducing Unauthorized Data Recovery from Solid-State Storage Devices
Phase Change Memory Cells Delineated by Regions of Modified Film Resistivity
Systems and Methods for Segmenting and Protecting a Storage Subystem
Patent:
7,912,991 →
Application:
12/409,174 →
Adjusting Access of Non-Volatile Semiconductor Memory Based on Access Time
Command Portal for Securely Communicating and Executing Non-Standard Storage Subsystem Commands
Patent:
8,375,151 →
Application:
12/425,992 →
Mechanically Decoupled Status Lens
Random Read and Read/Write Block Accessible Memory
Patent:
8,417,873 →
Application:
12/490,914 →
Methods for a Random Read and Read/Write Block Accessible Memory
Patent:
8,745,314 →
Application:
12/490,930 →
Network Computing Systems Having Shared Memory Clouds with Addresses of Disk-Read-Only Memories Mapped into Processor Address Spaces
Patent:
8,521,967 →
Application:
12/490,941 →
Supporting Variable Sector Sizes in Flash Storage Devices
Table Journaling in Flash Storage Devices
Redundant Data Distribution in a Flash Storage Device
High Speed Input/Output Performance in Solid State Devices
Enhanced Mlc Solid State Device
Slc-Mlc Combination Flash Storage Device
Flash Storage System and Method for Accessing a Boot Program
System and Method for Performing a Direct Memory Access at a Predetermined Address in a Flash Storage
Interleaved Flash Storage System and Method
System and Method of Maintaining Data Integrity in a Flash Storage Device
Flash Storage Device with Flexible Data Format
System and Method of Wear-Leveling in Flash Storage
Flash Memory Allocation for Improved Performance and Endurance
Tunneling Magnetoresistive (Tmr) Device with Improved Ferromagnetic Underlayer for Mgo Tunneling Barrier Layer
Parallel Data Storage System
Non-Volatile Semiconductor Memory Segregating Sequential, Random, and System Data to Reduce Garbage Collection for Page Based Mapping
Non-Volatile Semiconductor Memory Compressing Data to Improve Performance
Patent:
8,135,903 →
Application:
12/610,129 →
Data Storage System Comprising a Mapping Bridge for Aligning Host Block Size with Physical Block Size of a Data Storage Device
Data Storage Device Employing Data Path Protection Using Both Lba and Pba
Patent:
8,397,107 →
Application:
12/636,614 →
Implementing Data Storage and Dual Port, Dual-Element Storage Device
Systems and Methods for Measuring the Useful Life of Solid-State Storage Devices
Non-Volatile Semiconductor Memory Segregating Sequential Data During Garbage Collection to Reduce Write Amplification
Patent:
8,316,176 →
Application:
12/707,552 →
Non-Volatile Semiconductor Memory Storing an Inverse Map for Rebuilding a Translation Table
Patent:
8,407,449 →
Application:
12/714,350 →
Electronic Display Assembly Comprising a Display Mount and a Flex Circuit Wrapped Around and Adhered to the Display Mount
Patent:
8,358,395 →
Application:
12/720,602 →
Vertical Switch Three-Dimensional Memory Array
Multi-Interface and Multi-Bus Structured Solid-State Storage Subsystem
System and Method for Managing the Execution of Memory Commands in a Solid-State Memory
Patent:
8,725,931 →
Application:
12/732,951 →
Managing Wear Leveling and Garbage Collection Operations in a Solid-State Memory Using Linked Lists
Patent:
8,713,066 →
Application:
12/749,329 →
Storage of Data Reference Blocks and Deltas in Different Storage Devices
Method for Providing Asynchronous Event Notification in Systems
System and Method for Managing Execution of Internal Commands and Host Commands in a Solid-State Memory
Patent:
8,782,327 →
Application:
12/777,771 →
Flash Storage Device with Read Disturb Mitigation
Flash Storage Device with Read Cache
Transferring Media Files Between Users After Encrypting with Encryption Key Obtained from a Digital Rights Management Server
Patent:
10,289,809 →
Application:
12/781,365 →
System and Method for Performing Data Retention in Solid-State Memory Using Copy Commands and Validity and Usage Data
Patent:
8,612,669 →
Application:
12/824,434 →
System and Method for Managing Data Access in Non-Volatile Memory
Patent:
8,447,920 →
Application:
12/825,779 →
System and Method for Optimizing Garbage Collection in Data Storage
Patent:
8,521,972 →
Application:
12/827,931 →
Data Storage Apparatus Providing Host Full Duplex Operations Using Half Duplex Storage Devices
Patent:
8,762,682 →
Application:
12/830,263 →
Systems and Apparatus for Main Memory
System and Apparatus with a Memory Controller Configured to Control Access to Randomly Accessible Non-Volatile Memory
Methods for Main Memory with Non-Volatile Type Memory Modules
Data Storage System with Compression/Decompression
Solid State Storage Device with Removable Power Backup
Solid-State Storage Device with Multi-Level Addressing
Methods and Systems for a Personal Multimedia Content Archive
Visual Indicator of Online Backup
Patent:
8,713,265 →
Application:
12/887,341 →
System and Method for Improving Wear-Leveling Performance in Solid-State Memory
Patent:
8,612,804 →
Application:
12/895,691 →
Current-Perpendicular-To-The-Plane (Cpp) Magnetoresistive Sensor with Cofege Ferromagnetic Layers and Ag or Agcu Spacer Layer
Diagonally accessed memory array circuit
Data Management in Flash Memory Using Probability of Charge Disturbances
Data management in flash memory using probability of charge disturbances
Early Detection of Degradation in nor Flash Memory
Early degradation detection in flash memory using test cells
System and Method for a Data Reliability Scheme in a Solid State Memory
Patent:
8,601,313 →
Application:
12/966,892 →
System and Method for Maintaining a Data Redundancy Scheme in a Solid State Memory in the Event of a Power Loss
System and Method for Using Over-Provisioned Data Capacity to Maintain a Data Redundancy Scheme in a Solid State Memory
Sequential Write Thread Detection
Patent:
8,458,435 →
Application:
12/973,085 →
System and Method for Optimized Management of Operation Data in a Solid-State Memory
Patent:
9,268,646 →
Application:
12/974,234 →
Selectively Enabling a Host Transfer Interrupt
Concurrently Searching Multiple Devices of a Non-Volatile Semiconductor Memory
System and Method for Data Error Recovery in a Solid State Subsystem
Patent:
8,700,950 →
Application:
13/025,980 →
System and Method for Improving a Data Redundancy Scheme in a Solid State Subsystem with Additional Metadata
Patent:
8,700,951 →
Application:
13/044,400 →
Apparatus and Method for Determining an Operating Condition of a Memory Cell Based on Cycle Information
Systems and Methods for Segmenting and Protecting a Storage Subsystem
Patent:
8,127,048 →
Application:
13/052,017 →
Power-Safe Data Management System
Flash Memory Device Comprising Host Interface for Processing a Multi-Command Descriptor Block in Order to Exploit Concurrency
Apparatus and Method for Determining a Read Level of a Memory Cell Based on Cycle Information
Non-Volatile Semiconductor Memory Module Enabling Out of Order Host Command Chunk Media Access
System and Method for Improved Parity Determination Within a Data Redundancy Scheme in a Solid State Memory
Storage System Bus Transfer Optimization
Patent:
8,751,728 →
Application:
13/098,357 →
System and Method for Data Recovery in a Solid State Storage Device
Patent:
8,503,237 →
Application:
13/110,662 →
Trellis-Coded Modulation in a Multi-Level Cell Flash Memory Device
Means and Method for Operating a Resistive Array
Patent:
8,934,293 →
Application:
13/135,235 →
Solid-State Drive with Reduced Power Up Time
Patent:
8,793,429 →
Application:
13/152,645 →
Mapping Table for Improving Write Operation Efficiency
Patent:
8,924,629 →
Application:
13/155,189 →
Self-Contained Placement of Data Objects in a Data Storage System
System and Method for Performing Data Retention That Incorporates Environmental Conditions
Memory Apparatus for Early Write Termination and Power Failure
Patent:
8,677,037 →
Application:
13/163,461 →
Methods for Early Write Termination and Power Failure with Non-Volatile Memory
Patent:
8,516,172 →
Application:
13/163,481 →
Methods for Early Write Termination into Non-Volatile Memory with Metadata Write Operations
Patent:
8,429,318 →
Application:
13/163,493 →
Replaceable Non-Volatile Memory Apparatus with a Plurality of Pluggable Electrical Connectors
Patent:
8,706,932 →
Application:
13/163,544 →
Memory Apparatus for Replaceable Non-Volatile Memory
Patent:
8,639,863 →
Application:
13/163,561 →
Methods for Upgrading, Diagnosing, and Maintaining Replaceable Non-Volatile Memory
Patent:
8,650,343 →
Application:
13/163,571 →
Methods for Data Redundancy Across Replaceable Non-Volatile Memory Storage Devices
Patent:
8,689,042 →
Application:
13/163,581 →
Background Selection of Voltage Reference Values for Performing Memory Read Operations
Patent:
8,638,602 →
Application:
13/167,032 →
Prioritized Access for Media with Heterogeneous Access Rates
Patent:
9,003,101 →
Application:
13/172,737 →
System and Method for Improving Wear-Leveling Performance in Solid-State Memory
Patent:
8,898,373 →
Application:
13/172,772 →
System and Method for Determining Data Dependent Noise Calculation for a Flash Channel
Apparatus and Method for Multi-Mode Operation of a Flash Memory Device
Apparatus and Method for Determining an Operating Condition of a Memory Cell Based on Cycle Information
Apparatus and Method for Determining a Read Level of a Flash Memory After an Inactive Period of Time
Unified Switch Array for Memory Devices
Patent:
8,378,456 →
Application:
13/199,437 →
System and Method for Reducing Contentions in Solid-State Memory Access
Patent:
8,769,190 →
Application:
13/214,132 →
Non-Volatile Storage Subsystem with Energy-Based Performance Throttling
Patent:
8,788,779 →
Application:
13/216,177 →
System and Method for High Performance Command Processing in Solid State Drives
Patent:
8,423,722 →
Application:
13/219,555 →
Asymmetric Log-Likelihood Ratio for Mlc Flash Channel
Interleaved Flash Storage System and Method
System and Method for Concurrently Executing Data Access Requests
Patent:
8,938,583 →
Application:
13/298,272 →
Methods and Systems for Object Level De-Duplication for Solid State Devices
Self Retaining Elastomeric Seal
Patent:
9,892,762 →
Application:
13/308,423 →
Translating Memory Modules for Main Memory
Data Storage Device Employing Cascaded Voltage Regulators During Power Failure
Patent:
8,767,354 →
Application:
13/314,475 →
Automatic and on-Demand Testing of Non-Volatile Storage Devices
Patent:
8,806,283 →
Application:
13/327,535 →
Memory Defect Management Using Signature Identification
Patent:
8,959,416 →
Application:
13/328,863 →
Accelerated Translation Power Recovery
Patent:
8,819,367 →
Application:
13/330,426 →
Solid State Drive Power Safe Wear-Leveling
Patent:
8,478,930 →
Application:
13/335,194 →
Loading Different Device Drivers for One Device
Patent:
8,832,327 →
Application:
13/335,515 →
Solid-State Storage Subsystem Security Solution
Patent:
9,251,381 →
Application:
13/339,812 →
Low Density Parity Check Code Decoding System and Method
High Current Capable Access Device for Three-Dimensional Solid-State Memory
Methods, Devices and Systems for Content Discovery, Aggregation and Presentment Over a Network
Patent:
8,868,666 →
Application:
13/359,371 →
Implementing Enhanced Data Write for Multi-Level Cell (Mlc) Memory Using Threshold Voltage-Drift or Resistance Drift Tolerant Moving Baseline Memory Data Encoding
Implementing Enhanced Data Read for Multi-Level Cell (Mlc) Memory Using Threshold Voltage-Drift or Resistance Drift Tolerant Moving Baseline Memory Data Encoding
Implementing Enhanced Data Partial-Erase for Multi-Level Cell (Mlc) Memory Using Threshold Voltage-Drift or Resistance Drift Tolerant Moving Baseline Memory Data Encoding
Erase-Suspend System and Method
Pre-Cache Similarity-Based Delta Compression for Use in a Data Storage System
Network Attached Storage (Nas) Protection Meter and Methods for Alerting Users of the State of Protection of a Nas
Patent:
9,122,417 →
Application:
13/367,273 →
Methods and Devices for Authentication and Data Encryption
Systems and Methods for Measuring the Useful Life of Solid-State Storage Devices
Isolation Devices for High Performance Solid State Drives
Drive Bias and Damping for Trayless Disk Drive Enclosures
Patent:
8,902,579 →
Application:
13/409,008 →
Auto Calibration of Storage Memory Controller
Patent:
8,379,457 →
Application:
13/420,849 →
Transmission Error Detector for Flash Memory Controller
Multi-Interface and Multi-Bus Structured Solid-State Storage Subsystem
Patent:
8,433,858 →
Application:
13/425,303 →
Mechanism to Manage Access to User Data Area with Bridged Direct-Attached Storage Devices
Patent:
8,646,054 →
Application:
13/429,094 →
Shock Mount and Retainer for a Disk Drive Enclosure
Patent:
8,462,460 →
Application:
13/434,772 →
Mram-Based Security for Data Storage Systems
Patent:
8,909,942 →
Application:
13/436,327 →
Redundant Power Backplane for Nas Storage Device
Patent:
9,535,472 →
Application:
13/436,849 →
Managing Memory Systems Containing Components with Asymmetric Characteristics
Asymmetric Memory Migration in Hybrid Main Memory
Integrating Data from Symmetric and Asymmetric Memory
Managing Unreliable Memory in Data Storage Systems
Methods of Flash Dual Inline Memory Modules with Flash Memory
Digital Rights Managment System, Devices, and Methods for Binding Content to an Intelligent Storage Device
Digital Rights Management System and Methods for Accessing Content from an Intelligent Storage
Digital Rights Management System and Methods for Provisioning Content to an Intelligent Storage
Digital Rights Management System Transfer of Content and Distribution
Using Non-Volatile Memory Resources to Enable a Virtual Buffer Pool for a Database Application
Patent:
8,478,931 →
Application:
13/465,790 →
System Data Management Using Garbage Collection and Hybrid Self Mapping
Patent:
8,966,205 →
Application:
13/468,946 →
Storing and Reconstructing Mapping Table Data in a Data Storage System
Patent:
8,984,247 →
Application:
13/468,999 →
System Data Management Using Garbage Collection and Logs
Patent:
9,977,612 →
Application:
13/470,206 →
Solid-State Device with Load Isolation
Methods for Optimizing Data Movement in Solid State Devices
Garbage Collection Based on the Inactivity Level of Stored Data
Patent:
8,788,778 →
Application:
13/488,249 →
Managing Memory Systems Containing Components with Asymmetric Characteristics
High Speed Hard Ldpc Decoder
Seamless Application Access to Hybrid Main Memory
Reduced Memory Multi-Channel Parallel Encoder System
Patent:
8,347,200 →
Application:
13/526,446 →
Flash Storage Device with Data Integrity Protection
System and Method of Using Stripes for Recovering Data in a Flash Storage System
Efficient Error Handling Mechanisms in Data Storage Systems
Patent:
8,924,832 →
Application:
13/533,152 →
Mechanisms for Efficient Management of System Data in Data Storage Systems
Patent:
8,954,653 →
Application:
13/533,529 →
Optimal Programming Levels for Ldpc
Secure Memory Devices and Methods of Managing Secure Memory Devices
Managing Security in Solid-State Devices
Solid-State Drive Retention Monitor Using Reference Blocks
Efficient Retry Mechanism for Solid-State Memory Failures
Patent:
8,788,880 →
Application:
13/592,218 →
Methods, Data Storage Devices and Systems Having Variable Size Ecc Page Size
Patent:
8,898,548 →
Application:
13/594,696 →
Integrated Storage and Switching for Memory Systems
Motherboard with Card Guide Cutouts
Chassis with Separate Thermal Chamber for Solid State Memory
Wear Leveling in Solid-State Device
Handling Writes to a Memory Including Asymmetric and Symmetric Components
Reducing a Number of Close Operations on Open Blocks in a Flash Memory
Optimizing Signature Computation and Sampling for Fast Adaptive Similarity Detection Based on Algorithm-Specific Performance
Methods for Managing Cache Configuration
Patent:
8,560,775 →
Application:
13/631,463 →
Techniques For Storing Data in Stuck and Unstable Memory Cells
Techniques For Storing Data in Stuck Memory Cells
Encoding and Decoding Data to Accommodate Memory Cells Having Stuck-At Faults
Adaptive Error Correction Codes for Data Storage Systems
Apparatus and Method for Programming a Multi-Level Phase Change Memory (Pcm) Cell Based on an Actual Resistance Value and a Reference Resistance Value
Out-Of-Order Data Transfer Mechanisms for Data Storage Systems
Patent:
10,095,433 →
Application:
13/659,865 →
System and Method to Cache Hypervisor Data
Systems and Methods for Managing Key-Value Stores
Patent:
8,612,402 →
Application:
13/662,200 →
Optimized Garbage Collection Algorithm to Improve Solid State Drive Reliability
Non-Volatile Semiconductor Memory Storing an Inverse Map for Rebuilding a Translation Table
Patent:
8,489,854 →
Application:
13/670,228 →
Methods and Devices for Avoiding Lower Page Corruption in Data Storage Devices
Methods, Data Storage Devices and Systems for Fragmented Firmware Table Rebuild in a Solid State Drive
Method and System for Hash Key Memory Footprint Reduction
Dynamic Ldpc Code Rate Solution
Reliable Physical Unclonable Function for Device Authentication
Methods for Managing Failure of a Solid State Device in a Caching Storage
System and Method for Lower Page Data Recovery in a Solid State Drive
Techniques For Encoding and Decoding Using a Combinatorial Number System
Techniques for Storing Bits in Memory Cells Having Stuck-at Faults
Dynamically Assigning Inactive Pages Not Used in Reed-Solomon Code in Non-Volatile Solid-State Storage Array
Patent:
9,026,893 →
Application:
13/713,561 →
Bipolar-MOS Memory Circuit
Multi-Layer Input/Output Pad Ring for Solid State Device Controller
System and Method for Storing Data Using a Flexible Data Format
Electronic Enclosure with Top-Facing Venting
Patent:
8,981,218 →
Application:
13/723,079 →
Word-Line Inter-Cell Interference Detector in Flash System
Inter-Cell Interference Algorithms for Soft Decoding of Ldpc Codes
System and Method for Reducing Memory in a Multi-Channel Parallel Encoder System
Programming Algorithm for Improved Flash Memory Endurance and Retention
Systems and Methods of Configuring a Mode of Operation in a Solid-State Memory
Decoder Supporting Multiple Code Rates and Code Lengths for Data Storage Systems
Patent:
8,966,339 →
Application:
13/742,243 →
Decoder Having Early Decoding Termination Detection
Patent:
9,619,317 →
Application:
13/742,248 →
Methods for Early Write Termination with Non-Volatile Memory
Patent:
8,850,091 →
Application:
13/745,804 →
Systems and Methods for Auto-Calibration of a Storage Memory Controller
Data Storage System with Primary and Secondary Compression Engines
Methods, Solid State Drive Controllers and Data Storage Devices Having a Runtime Variable Raid Protection Scheme
Systems and Methods for Providing Load Isolation in a Solid-State Device
Reduced Complexity Non-Binary Ldpc Decoding Algorithm
Thermal Regulation for Solid State Memory
Adjusting Operating Parameters for Memory Cells Based on Wordline Address and Cycle Information
Determining Bias Information for Offsetting Operating Variations in Memory Cells Based on Wordline Address
Secure Access to Shared Storage Resources
Soft-Decision Input Generation for Data Storage Systems
Patent:
8,924,824 →
Application:
13/797,923 →
Soft-Decision Input Generation for Data Storage Systems
Patent:
10,061,640 →
Application:
13/797,943 →
Optimizing Data Block Size for Deduplication
Overprovision Capacity in a Data Storage Device
Decoding Data Stored in Solid-State Memory
Thermal Control of a Storage Device Receiving a Limited Amount of Power
Patent:
9,158,366 →
Application:
13/829,955 →
Methods and Controllers for Controlling a Data Storage Device and Data Storage Device Comprising the Same
Patent:
9,554,110 →
Application:
13/838,535 →
Managing the Write Performance of an Asymmetric Memory System
System and Method of Processing of Duplicate Data at a Data Storage Device
System and Method to Improve Enterprise Reliability Through Tracking I/O Performance Metrics in Non-Volatile Random Access Memory
Patent:
9,842,660 →
Application:
13/841,026 →
Dynamic Restriping in Nonvolatile Memory Systems
Patent:
9,286,002 →
Application:
13/841,706 →
Power Arbitration for Storage Devices
System and Method for Error-Minimizing Voltage Threshold Selection
Patent:
9,542,258 →
Application:
13/842,771 →
Small Block Write Operations in Non-Volatile Memory Systems
Patent:
8,996,796 →
Application:
13/842,940 →
System and Method for Dynamic Scaling of Ldpc Decoder in a Solid State Drive
Patent:
9,059,742 →
Application:
13/842,956 →
System and Method for Scanning Flash Memories
Soft Information Module
Systems and Methods of Using Dynamic Data for Wear Leveling in Solid-State Devices
System and Method for Accessing and Storing Interleaved Data
Read Level Adjustment Using Soft Information
Multiple Stream Compression and Formatting of Data for Data Storage Systems
Storage System Comprising a Communications Port for Charging an Electronic Device
Patent:
9,891,693 →
Application:
13/902,722 →
Thermal Management for Solid-State Drive
Thermal Interface Material Pad and Method of Forming the Same
Performance Improvement for Attached Multi-Storage Devices
Patent:
8,943,237 →
Application:
13/925,746 →
Managing the Write Performance of an Asymmetric Memory System
Managing the Write Performance of an Asymmetric Memory System
Methods and Devices for Booting a Network Attached Storage with Two Logical Units
Using Non-Volatile Memory Resources to Enable a Virtual Buffer Pool for a Database Application
Patent:
9,436,597 →
Application:
13/932,534 →
System and method for data recovery in a solid state storage device using optimal reference voltage values of a related storage element
Patent:
8,861,272 →
Application:
13/935,221 →
Chunk-Level Client Side Encryption in Hierarchical Content Addressable Storage Systems
System and Method for Optimizing Garbage Collection in Data Storage
Patent:
8,706,985 →
Application:
13/948,495 →
Implementing Enhanced Buffer Management for Data Storage Devices
Method and Apparatus for Cooling Components in an Electronic Device
Patent:
10,120,351 →
Application:
13/957,814 →
Backup Power for Reducing Host Current Transients
Fast Saving of Data During Power Interruption in Data Storage Systems
Patent:
9,830,257 →
Application:
13/967,292 →
Methods of Communicating to Different Types of Memory Modules in a Memory Channel
Methods for Accessing Memory in a Two-Dimensional Main Memory Having a Plurality of Memory Slices
Multi-Chip Packaged Integrated Circuit with Flash Memory and Slave Memory Controller
Multi-Chip Packaged Flash Memory/Support Application Specific Integrated Circuit for Flash Dual Inline Memory Modules
Flash Dual Inline Memory Modules with Multiplexing Support Circuits
High Performance System Providing Selective Merging of Dataframe Segments in Hardware
Power Fail Protection and Recovery Using Low Power States in a Data Storage Device/System
Data Retention Monitoring Using Temperature History in Solid State Drives
Patent:
9,165,668 →
Application:
14/026,017 →
Using Dual Phys to Support Multiple Pcie Link Widths
Automatic Start of an Application at Start Up for a Media Player Appliance
Patent:
9,569,229 →
Application:
14/028,295 →
Memory Unit Assignment and Selection for Internal Memory Operations in Data Storage Systems
Patent:
9,632,926 →
Application:
14/028,377 →
Systems and Methods for Improving Garbage Collection and Wear Leveling Performance in Data Storage Systems
Patent:
10,417,123 →
Application:
14/028,412 →
Asymmetric Memory Migration in Hybrid Main Memory
Negative Pool Management for Deduplication
Patent:
9,348,531 →
Application:
14/053,532 →
Method and System for Atomically Writing Scattered Information in a Solid State Storage Device
Patent:
9,170,938 →
Application:
14/060,547 →
Methods and Systems for Privileged Execution Support for File System Commands on a Storage Device
Writable Clone Data Structure
Captivating Shock Mounts for Data Storage Devices Using Retention Clips
Patent:
9,360,900 →
Application:
14/077,042 →
Apparatus and Method for Routing Information in a Non-Volatile Memory-Based Storage Device
Apparatus and Method for Accessing a Non-Volatile Memory Blade Using Multiple Controllers in a Non-Volatile Memory Based Storage Device
Navigating Through Media Object Collection
Implementing Enhanced Performance with Read Before Write to Phase Change Memory
Systems and Methods for Packaging High Density Ssds
Systems and Methods for Securing High Density Ssds
Self-Encrypting Data Storage Device Supporting Object-Level Encryption
Patent:
9,665,501 →
Application:
14/090,202 →
Memory Card Placement Within a Solid State Drive
Patent:
9,583,153 →
Application:
14/090,297 →
Early De-Allocation of Write Buffer in an Ssd
Patent:
9,170,939 →
Application:
14/090,596 →
Apparatus and Method for Translation from Multi-Dimensional to Linear Address Space in Storage
Apparatus and Method for Referencing Dense and Sparse Information in Multi-Dimensional to Linear Address Space Translation
Apparatus and Method for Using Fields in N-Space Translation of Storage Requests
Apparatus and Method for Insertion and Deletion in Multi-Dimensional to Linear Address Space Translation
Apparatus and Method for Cloning and Snapshotting in Multi-Dimensional to Linear Address Space Translation
Acoustically Secure Phase Change Memory Devices
Search of Nas Data Through Association of Errors
Patent:
9,864,781 →
Application:
14/099,863 →
Method and System for Soft Decoding Through Single Read
Patent:
9,270,296 →
Application:
14/100,435 →
Programming Scheme for Improved Voltage Distribution in Solid-State Memory
Compressor Resources for High Density Storage Units
Data Storage Device Supporting Accelerated Database Operations
Power Sequencing and Data Hardening Architecture
Startup Performance and Power Isolation
Hard Power Fail Architecture
Location-Aware Behavior for a Data Storage Device
Patent:
9,612,744 →
Application:
14/137,537 →
Optimized N-Stream Sequential Media Playback Caching Method and System
Patent:
9,871,882 →
Application:
14/146,194 →
Power Conservation Based on Caching
Random Number Generator by Superparamagnetism
Memory Apparatus and Methods Thereof for Preventing Read Errors on Weak Pages in a Non-Volatile Memory System
Shutdowns and Data Recovery to Avoid Read Errors Weak Pages in a Non-Volatile Memory System
Data Transfer by Data Storage Device Based on Received Uniform Resource Locator Information
Patent:
10,601,895 →
Application:
14/195,079 →
Vertically Integrated Storage
Mass Storage Device and Method of Operating the Same to Back Up Data Stored in Volatile Memory
Mass Storage Device and Method of Operating the Same to Store Parity Data
High Density Server Storage Unit
System and Method for Data Error Recovery in a Solid State Subsystem
Patent:
9,405,617 →
Application:
14/216,295 →
On-The-Fly Media-Tagging, Media-Uploading and Media Navigating by Tags
Patent:
9,614,894 →
Application:
14/230,753 →
Non-Binary Ldpc Decoder Using Binary Subgroup Processing
Patent:
9,337,864 →
Application:
14/231,511 →
Non-Binary Low-Density Parity Check (Ldpc) Decoding Using Trellis Maximization
Patent:
9,250,994 →
Application:
14/231,531 →
Content Matching System for a Networked Media Player
Local Area Network Distributed Storage
Patent:
9,626,376 →
Application:
14/244,672 →
Storage Cartridge Dock System
Partial Garbage Collection for Fast Error Handling and Optimized Garbage Collection for the Invisible Band
Patent:
9,354,955 →
Application:
14/250,000 →
Flash Storage Device with Read Disturb Mitigation
System and Method for Reducing Contentions in Solid-State Memory Access
Patent:
9,652,379 →
Application:
14/266,520 →
Method and Apparatus for Restricting Writes to Solid State Memory When an End-of-Life Condition Is Reached
Shroud for an Electronic Device
Patent:
9,699,923 →
Application:
14/275,363 →
System and Method for Caching Solid State Device Read Request Results
Device Pairing Over Different Networks
Patent:
10,091,694 →
Application:
14/287,421 →
System and Method of Interleaving Data Retrieved from First and Second Buffers
Notification Propagation in Virtual Computing Environment
Patent:
9,189,264 →
Application:
14/299,332 →
Non-Volatile Storage Subsystem with Energy-Based Performance Throttling
Patent:
9,182,916 →
Application:
14/306,070 →
Embedded Non-Volatile Memory
Solid-State Memory Corruption Mitigation
Word-Line Inter-Cell Interference Detector in Flash System
Self-Aligning Bracket Assembly
Patent:
9,265,171 →
Application:
14/314,942 →
System and Method of Updating Metablocks Associated with Multiple Memory Dies
High Capacity Storage Unit
Implementing Enhanced Performance with Read Before Write to Phase Change Memory to Avoid Write Cancellations
Multiple Ecc Codeword Sizes in an Ssd
Hand Held Storage Device
Patent:
10,068,619 →
Application:
14/341,653 →
Storage System with Reduced Hash Key Memory
Systems and Methods for Read Caching in Flash Storage
Address Translation for a Non-Volatile Memory Storage Device
Doorbell-Less Endpoint-Initiated Protocol for Storage Devices
Ack-Less Protocol for Noticing Completion of Read Requests
Latency Command Processing for Solid State Drive Interface Protocol
Memory Channel Connected Non-Volatile Memory
Temperature Compensation Management in Solid-State Memory
Patent:
9,275,741 →
Application:
14/482,852 →
Acknowledgement-Less Protocol for Solid State Drive Interface
Doorbell-Less Protocol for Solid State Drive Interface
Data Storage Devices with Performance-Aware Power Capping
Drive Compatibility Information Maintenance
Patent:
9,569,112 →
Application:
14/497,272 →
Managing and Accessing Data Storage Systems
Patent:
9,866,634 →
Application:
14/498,320 →
Multi-Tier Scheme for Logical Storage Management
Read Writeable Randomly Accessible Non-Volatile Memory Modules
Offline Deduplication for Solid-State Storage Devices
Optimized Garbage Collection for Solid-State Storage Devices
Methods for Early Write Termination with Non-Volatile Memory
Patent:
9,727,112 →
Application:
14/500,980 →
System and Method to Provide File System Functionality Over a Pcie Interface
Performance Acceleration During Shutdown of a Data Storage Device
Method of Optimizing Device Performance by Maintaining Device Within Temperature Limits
Communications Device That Logically Connects an Upstream Signal Line to a Downstream Signal Line
Patent:
9,911,011 →
Application:
14/547,462 →
Real Time Protocol Generation
Read Level Grouping Algorithms for Increased Flash Performance
Calibrating Optimal Read Levels
Three-Dimensional Magnetic Memory with Multi-Layer Data Storage Layers
Systems and Methods for Adaptive Error Corrective Code Mechanisms
Systems and Methods for Multi-Zone Data Tiering for Endurance Extension in Solid State Drives
Spin Transfer Torque Tunneling Magnetoresistive Device Having a Laminated Free Layer with Perpendicular Magnetic Anisotropy
Patent:
9,236,560 →
Application:
14/563,721 →
Methods and Systems for Implementing Redundancy in Memory Controllers
Programmable Solid State Drive Controller and Method for Scheduling Commands Utilizing a Data Structure
Adaptive Error Correction Codes for Data Storage Systems
Digital Rights Management System Transfer of Content and Distribution
Patent:
9,424,400 →
Application:
14/571,178 →
Throttling Command Execution in Non-Volatile Memory Systems Based on Power Usage
Providing Digital Video Assets with Multiple Age Rating Levels
Soft-Decision Input Generation for Data Storage Systems
Patent:
10,545,819 →
Application:
14/584,326 →
Apparatus, Systems, and Methods for Data Recovery
Performance Tuning for Storage Devices
Managing Wear of System Areas of Storage Devices
Reduced Complexity Non-Binary Ldpc Decoding Algorithm
File Management System
Read and Write Access Performance for Non-Volatile Memory
Patent:
9,213,637 →
Application:
14/613,345 →
Secure Stream Buffer on Network Attached Storage
Geometry Aware Block Reclamation
Adaptive Targeting of Read Levels in Storage Devices
Hybrid Solid State Drive (Ssd) Using Pcm or Other High Performance Solid-State Memory
Apparatus, Systems, and Methods for Operating Flash Backed Dram Module
Error Correction for Non-Volatile Memory
Encoding Scheme for 3D Vertical Flash Memory
Bipolar-Mos Memory Circuit
System and Method for Copy on Write on an Ssd
Doorless Protocol Having Multiple Queue Read Requests in Flight
Methods and Devices for Booting a Network Attached Storage with Two Logical Units
Patent:
9,479,588 →
Application:
14/632,085 →
Methods and Systems to Reduce Ssd Io Latency
Controlling Coupling in Large Cross-Point Memory Arrays
Patent:
9,349,447 →
Application:
14/635,532 →
Processing Data Storage Commands for Enclosure Services
Methods and Systems for Memory Page Allocation
Updating Exclusive-or Parity Data
Multi-Layer Pad Ring for Integrated Circuit
Controlling Encrypted Data Stored on a Remote Storage Device
Storage Drive Heat Sink Mounting Structure
Patent:
9,594,409 →
Application:
14/661,952 →
Read Level Grouping for Increased Flash Performance
Processing Data Access Requests from Multiple Interfaces for Data Storage Devices
Patent:
9,785,361 →
Application:
14/667,470 →
Small Block Write Operations in Non-Volatile Memory Systems
Patent:
9,304,908 →
Application:
14/667,804 →
Data Storage Device Providing Data Maintenance Services
Patent:
10,444,998 →
Application:
14/673,392 →
Symmetric and Continuous Media Stream from Multiple Sources
Patent:
9,942,294 →
Application:
14/673,544 →
Communication Interface Initialization
Hybrid Analog and Digital Memory Device
Boundary Scan Testing a Storage Device via System Management Bus Interface
Task Queues
High Performance Read-Modify-Write System Providing Line-Rate Merging of Dataframe Segments in Hardware
Patent:
9,948,322 →
Application:
14/698,766 →
System and Method for Lower Page Data Recovery in a Solid State Drive
Patent:
9,952,939 →
Application:
14/700,760 →
High Speed Input/Output Performance in Solid State Devices
System and Method for Dynamic Scaling of Ldpc Decoder in a Solid State Drive
Patent:
9,350,391 →
Application:
14/722,673 →
System and Method for Caching Virtual Machine Data
Asymmetric Log-Likelihood Ratio for Flash Channel
Setting Operating Parameters for Memory Cells Based on Wordline Address and Cycle Information
Embedded Non-Volatile Memory
Data Storage Device Docking Station
Patent:
10,097,636 →
Application:
14/740,206 →
Apparatus and Method for Inline Compression and Deduplication
Apparatus and Method for Single Pass Entropy Detection on Data Transfer
Identifying Disk Drives and Processing Data Access Requests
Scheduling Scheme(S) for a Multi-Die Storage Device
Non-Volatile Memory with Adjustable Cell Bit Shape
Patent:
9,472,281 →
Application:
14/788,167 →
Electroplated Phase Change Switch
Flash Storage Device with Power Monitoring
Programming Algorithm for Improved Flash Memory Endurance and Retention
Nmos Regulated Voltage Reference
Optimized Garbage Collection Algorithm to Improve Solid State Drive Reliability
Managing Asymmetric Memory System as a Cache Device
Memory Modules with Multi-Chip Packaged Integrated Circuits Having Flash Memory
Thermal Management for Solid-State Drive
Licensable Function for Securing Stored Data
Fifo Buffer Clean-Up
Ejection Mechanism Assembly for Storage Drive and Storage Drive Having the Ejection Mechanism Assembly
Systems and Methods for a Mass Data Storage System Having a File-Based Interface to a Host and a Non-File-Based Interface to Secondary Storage
Systems and Methods for a Mass Data Storage System Having a File-Based Interface to a Host and a Non-File-Based Interface to Secondary Storage
Sharing Groups for Capturing Digital Media
Patent:
10,416,850 →
Application:
14/819,658 →
Correlating Physical Page Addresses for Soft Decision Decoding
Storing Parity Data Separate from Protected Data
Methods and Systems for Improving Flash Memory Flushing
Methods and Systems for Updating a Recovery Sequence Map
Implementing Enhanced Magnetic Memory Cell
Implementing Magnetic Memory Integration with Cmos Driving Circuits
Method and System for Hash Key Memory Reduction
4F2 Scr Memory Device
Tilted Synthetic Antiferromagnet Polarizer/Reference Layer for Stt-Mram Bits
Methods and Systems for a Portable Data Locker
Multi-Level Phase Change Device
Patent:
9,564,585 →
Application:
14/845,016 →
Operating Parameters for Flash Memory Devices
Temperature Management in Data Storage Devices
Method for Providing Nonvolatile Storage Write Bandwidth Using a Caching Namespace
Method for Providing Nonvolatile Storage Write Bandwidth Using a Caching Namespace
Synchronous Mirroring in Non-Volatile Memory Systems
System and Method for Performing Data Retention in Solid-State Memory Using an Lru List
Soft Information Module
Weighted Programming Patterns in Solid-State Data Storage Systems
Repair-Optimal Parity Code
Memory Die Temperature Adjustment Based on Aging Condition
Joint Decoding of Rewriting Nvm Error Sectors
Measuring Performance of Data Storage Systems
Data Retention Monitoring Using Temperature History in Solid State Drives
Mtj Memory Array Subgrouping Method and Related Drive Circuitry
System and Method for Dynamically Adjusting Garbage Collection Policies in Solid-State Memory
Planar Variable Resistance Memory
Storage of Data Reference Blocks and Deltas in Different Storage Devices
Scheduling Scheme(S) for a Multi-Die Storage Device
Bottom Pinned Sot-Mram Bit Structure and Method of Fabrication
Fabric Interconnection for Memory Banks Based on Network-on-Chip Methodology
System Data Storage Mechanism Providing Coherency and Segmented Data Loading
Data Storage Device and Method of Operation Using Multiple Security Protocols
Memory Health Monitoring
Multilayer 3D Memory Based on Network-on-Chip Interconnection
Error Location Pointers for Non Volatile Memory
Three Terminal Sot Memory Cell with Anomalous Hall Effect
Data Retention Charge Loss and Read Disturb Compensation in Solid-State Data Storage Systems
Data Retention Charge Loss Sensor
Systems and Methods for Adaptive Partitioning in Distributed Cache Memories
Storage Processing Unit Arrays and Methods of Use
Method of Decreasing Write Amplification of Nand Flash Using a Journal Approach
Orientation-Based Data Transfer
Patent:
10,289,337 →
Application:
14/945,240 →
Magnetoresistive Effect Devices Having Enhanced Magnetic Anisotropy
Patent:
9,564,581 →
Application:
14/948,145 →
Determining Bias Information for Offsetting Operating Variations in Memory Cells
Deposition Method for Planar Surfaces
Apparatus and Method for Routing Information in a Non-Volatile Memory-Based Storage Device
Efficient Error Handling Mechanisms in Data Storage Systems
Method for Forming Pcm and Rram 3-D Memory Cells
Generation of Random Address Mapping in Non-Volatile Memories Using Local and Global Interleaving
Memory Server with Read Writeable Non-Volatile Memory
Spin-Orbit Torque Bit Design for Improved Switching Efficiency
Providing Secure Access to Digital Storage Devices
Patent:
10,268,814 →
Application:
14/972,013 →
Methods for Managing Failure of a Solid State Device in a Caching Storage
Atomic Write Command Support in a Solid State Drive
Automated Latency Monitoring
Selective Buffer Protection
Library for Seamless Management of Storage Devices
Distributed Data Storage with Reduced Storage Overhead Using Reduced-Dependency Erasure Codes
Seamless Application Access to Hybrid Main Memory
Trim Command Processing in a Solid State Drive
Asymmetric Memory Migration in Hybrid Main Memory
Characterizing and Operating a Non-Volatile Memory Device
Patent:
9,620,227 →
Application:
14/991,484 →
Method and System for Efficient Common Processing in Memory Device Controllers
Method and System for a Common Processing Framework for Memory Device Controllers
Spin Transfer Torque Tunneling Magnetoresistive Device Having a Laminated Free Layer with Perpendicular Magnetic Anisotropy
Direct Interface Between Graphics Processing Unit and Data Storage Unit
Nano-Particle Matrix for 3D Nvm Rram
Method for Controlled Switching of a Mram Device
Synchronization Method and Apparatus for an Interconnection Network Using Parallel-Headerless Tdma Routing
Writable Clone Data Structure
Writable Clone Data Structure
Accelerated Atomic Resource Allocation on a Multiprocessor Platform
Data Retention Flags in Solid-State Drives
Inter-Cell Interference Reduction in Flash Memory Devices
Patent:
9,704,594 →
Application:
15/047,113 →
Method and Apparatus to Generate Zero Content Over Garbage Data When Encryption Parameters Are Changed
Using a Proprietary Framework on a Standards-Based Embedded Device
Adjustable Priority Ratios for Multiple Task Queues
Temperature Compensation Management in Solid-State Memory
Efficient Cross Device Redundancy Implementation on High Performance Direct Attached Non-Volatile Storage With Data Reduction
Method of Preventing Metadata Corruption by Using a Namespace and a Method of Verifying Changes to the Namespace
Apparatus and Method for Reducing Storage Class Memory Write-Backs
Memory Die Temperature Adjustment Based on Aging Condition
Intelligent Wide Port Phy Usage
Efficient and Dynamically Sized Reverse Map to Handle Variable Size Data
Data Storage Device, Method and System, and Control of Data Storage Device Based on Writing Operations and Lifetime
Dynamic Restriping in Nonvolatile Memory Systems
Patent:
9,811,285 →
Application:
15/067,284 →
Memory Cell Located Pulse Generator
Systems and Methods for Adaptive Read Level Adjustment
Redundancy of Error Correction Encoded Data in a Storage System
Power Management of Storage Devices
Data Reliability Information in a Non-Volatile Memory Device
Small Block Write Operations in Non-Volatile Memory Systems
Patent:
9,898,196 →
Application:
15/076,742 →
High Density Server Storage Unit
Managing the Write Performance of an Asymmetric Memory System
Patent:
9,588,698 →
Application:
15/077,282 →
Linear Push-Push Mechanism For Removable Storage Cartridge System
Insertion/Ejection Assist Mechanism For Removable Storage Cartridge System
Patent:
9,703,333 →
Application:
15/077,695 →
3D Cross-Point Memory Device
Patent:
9,735,151 →
Application:
15/080,525 →
Systems and Methods for Offloading Processing from a Host to Storage Processing Units Using an Interconnect Network
Systems and Methods for Packaging High Density Ssds
Solid State Memory Thermal Regulation
Methods and Systems for Implementing High Speed Serial Interface Bus Having Inhomogeneous Lane Bundles and Encodings
Memory Erase Management
Network Computer Systems with Power Management
Nano-Imprinted Self-Aligned Multi-Level Processing Method
Wear Leveling in Storage Devices
Dual Ots Memory Cell Selection Means and Method
Wear Leveling in Solid State Devices
Reduced Complexity Non-Binary Ldpc Decoding Algorithm
Front/Back Control of Integrated Circuits for Flash Dual Inline Memory Modules
Collision Detection for Slave Storage Devices
Generalized Verification Scheme for Safe Metadata Modification
Nonvolatile Bipolar Junction Memory Cell
Patent:
9,711,718 →
Application:
15/141,761 →
Residual Capacitance Performance Booster
Patent:
9,508,399 →
Application:
15/145,575 →
Diffused Resistive Memory Cell with Buried Active Zone
Generalized Write Operations Verification Method
Zoning of Logical to Physical Data Address Translation Tables with Parallelized Log List Replay
Apparatus and Method for Accessing a Non-Volatile Memory Blade Using Multiple Controllers in a Non-Volatile Memory Based Storage Device
Non-Binary Ldpc Decoder Using Binary Subgroup Processing
Host Read Command Return Reordering Based on Time Estimation of Flash Read Command Completion
System and Method for Direct Memory Access in a Flash Storage
Resistive Memory Device by Substrate Reduction
System and Method for Dynamic Scaling of Ldpc Decoder in a Solid State Drive
Partial Garbage Collection for Fast Error Handling and Optimized Garbage Collection for the Invisible Band
Temperature Variation Compensation
Power-Safe Data Management System
Fast Secure Erase in a Flash System
Solid State Devices Having Fine Pitch Structures
Compression and Caching for Logical-to-Physical Storage Address Mapping Tables
Ovonic Threshold Switch (Ots) Driver/Selector Uses Unselect Bias to Pre-Charge Memory Chip Circuit and Reduces Unacceptable False Selects
Bi-Directional Rram Decoder-Driver
Unified Paging Scheme for Dense and Sparse Translation Tables on Flash Storage Systems
Incremental Snapshot Based Technique on Paged Translation Systems
Translation Lookup and Garbage Collection Optimizations on Storage System with Paged Translation Table
Efficient Management of Paged Translation Maps In Memory and Flash
Implementing Deposition Growth Method for Magnetic Memory
Controlling Access to Namespaces of a Storage Device
Apparatus and Method for Determining an Operating Condition of a Memory Cell Based on Cycle Information
Systems and Methods for Classifying Data in Solid State Drives
Mapping Tables for Storage Devices
Systems and Methods for Programming Data to Storage Devices
Thermal Management of Selector
Memory Die Temperature Adjustment Based on a Power Condition
Managing Wear of System Areas of Storage Devices
Method and Apparatus to Generate Zero Content Over Garbage Data When Encryption Parameters Are Changed
Embedded Non-Volatile Memory
Signature-Based Service Manager with Dependency Checking
Error Detecting Code with Partial Update
Efficient Ram Usage in Computing Devices
Error Mitigation for 3D Nand Flash Memory
Random Number Generator by Superparamagnetism
Trim Management in Solid State Drives
Incremental Background Media Scan
Stream Management for Storage Devices
Methods, Devices and Systems for Two Stage Power-on Map Rebuild with Free Space Accounting in a Solid State Drive
Method for Fabricating Mram Bits on a Tight Pitch
System and Method for Managing Access Requests to a Memory Storage Subsystem
Methods and Devices for Booting a Network Attached Storage with Two Logical Units
Adaptive Wear Levelling
Hierarchical Variable Code Rate Error Correction Coding
Managing the Write Performance of an Asymmetric Memory System
Methods, Devices and Systems for Solid State Drive Control
Linked Storage System and Host System Error Correcting Code
Programmable Input/Output (Pio) Engine Interface Architecture with Direct Memory Access (Dma) for Multi-Tagging Scheme for Storage Devices
Invalidation Data Area for Cache
Content-Aware Filter Options for Media Object Collections
Implementing Magnetic Memory Pillar Design
Apparatus and Method for Single Pass Entropy Detection on Data Transfer
Method and Apparatus for Offloading Data Processing to Hybrid Storage Devices
Method and Apparatus for Monitoring Non-Volatile Memory Read Errors Using Background Media Scan
Non-Binary Eccs for Low Latency Read, Fractional Bits Per Cell of Nand Flash
Method and Apparatus for Low-Latency Read of Flash Storage Devices Using Fractional Bits Per Cell
Load Balancing by Dynamically Transferring Memory Range Assignments
Bad Page Management in Storage Devices
Data Management Based on I/O Traffic Profiling
Methods and Apparatus for Read Disturb Detection Based on Logical Domain
Semiconductor Device Including Stacked Die with Continuous Integral via Holes
Conditional Journal for Storage Class Memory Devices
Scheduling Access Commands for Data Storage Devices
Memory Write Verification Using Temperature Compensation
Processor in Non-Volatile Storage Memory
Processor in Non-Volatile Storage Memory
Methods and Apparatus for Read Disturb Detection and Handling
Garbage Collection Read Throttling
Encoder Supporting Multiple Code Rates and Code Lengths
Patent:
9,838,033 →
Application:
15/396,366 →
Tapered Variable Node Memory
Error Recovery Handling
Method and System for Managing Non-Volatile Memory
Recovery of Validity Data for a Data Storage System
Retiring Computer Memory Blocks
Memory Apparatus and Methods Thereof for Write Amplification Aware Wear Leveling
Overlapping Write Schemes for Cross-Point Non-Volatile Memory Devices
Patent:
9,911,494 →
Application:
15/403,800 →
Multi-Level Phase Change Device
Ecc Adjustment Based on Dynamic Error Information
Delayed Data Release After Programming To Reduce Read Errors In Memory
Method for Forming Pcm and Rram 3-D Memory Cells
Corruption-Preventative Programming in Solid-State Data Storage
Block Erase Schemes for Cross-Point Non-Volatile Memory Devices
Patent:
9,928,907 →
Application:
15/418,178 →
System and Method for Implementing Super Word Line Zones in a Memory Device
Coherent Controller
Read Operation and Soft Decoding Timing
Soft Decoding Scheduling
System and Methodology for Low Latency Error Management Within a Shared Non-Volatile Memory Architecture
Non-Volatile Storage Device with Physical Authentication
Calibrating Optimal Read Levels
Multi-Tier Scheme for Logical Storage Management
Access Network for Address Mapping in Non-Volatile Memories
Data Buffer Pointer Fetching For Direct Memory Access
Vertically Integrated Storage
Non-Volatile Memory with Program Failure Recovery
Patent:
10,019,332 →
Application:
15/456,237 →
Storage Drive Heat Sink Mounting Structure
Error Locator Polynomial Decoder and Method
Storage System and Method for Thermal Throttling via Command Arbitration
Atomic Write Command Support in a Solid State Drive
Apparatus and Method for Using Fields in N-Space Translation of Storage Requests
Capacity-Aware Wear Leveling in Solid-State Storage Devices
Location-Aware Behavior for a Data Storage Device
Error Correction for Non-Volatile Memory
Storage System and Method for Predictive Block Allocation for Efficient Garbage Collection
Protection Against State Transition Errors in Solid-State Data Storage Systems
Selecting Reversible Resistance Memory Cells Based on Initial Resistance Switching
Patent:
9,837,153 →
Application:
15/468,512 →
System and Method for Dynamic and Adaptive Interrupt Coalescing
System and Methodology for Error Management Within a Shared Non-Volatile Memory Architecture Using Bloom Filters
Apparatus and Method for Insertion and Deletion in Multi-Dimensional to Linear Address Space Translation
Managing I/O Operations of Large Data Objects in a Cache Memory Device by Dividing into Chunks
Post Write Erase Conditioning
Data Mapping Enabling Fast Read Multi-Level 3D Nand to Improve Lifetime Capacity
Thermal Throttling for Memory Devices
Calculating the Optimal Number of Lbns to Prefetch Per Cpu
Allocating Shared Memory Among Multiple Tasks in a Multiprocessor Environment
Storage System and Method for Thin Provisioning
Nano-Imprinted Self-Aligned Multi-Level Processing Method
Characterizing and Operating a Non-Volatile Memory Device
Patent:
10,068,650 →
Application:
15/484,038 →
Methods and Systems for Implementing Redundancy in Memory Controllers
Data Retention Flags in Solid-State Drives
Optimizing Data Block Size for Deduplication
Apparatus with a Memory Controller Configured to Control Access to Randomly Accessible Non-Volatile Memory
Address Translation for a Non-Volatile Memory Storage Device
Bit Reordering for Memory Devices
Method of Forming a Magnetic Head
Managing Data in a Storage System
Memory Unit Assignment and Selection for Internal Memory Operations in Data Storage Systems
System and Method for Locality Detection to Identify Read or Write Streams in a Memory Device
Multi-Layer Integrated Zone Partition System Error Correction
Storage System and Method for Handling Overheating of the Storage System
Storage System and Method for Bad Block Recycling
System and Method for Processing and Arbitrating Submission and Completion Queues
System and Method for Processing Non-Contiguous Submission and Completion Queues
System and Method for Speculative Execution of Commands Using a Controller Memory Buffer
Decoding Optimization for Channel Mismatch
Preserving Data Upon a Power Shutdown
Differential Signal Mismatch Compensation
Patent:
10,033,524 →
Application:
15/596,524 →
Mismatch Compensation at Differential Signal Receiver
Managing Phys of a Data Storage Target Device
Managing Phys of a Data Storage Target Device
Context-Aware Dynamic Command Scheduling for a Data Storage System
Run-Time Flash Die Failure Detection Enhancement
Temperature-Based Data Refreshing
System and Method for Adaptive Early Completion Posting Using Controller Memory Buffer
Reference Set Construction for Data Deduplication
Priority-Based Internal Data Movement
Physical Secure Erase of Solid State Drives
Systems and Methods for Controlling Metapage Storage on Data Storage Devices
Managing I/O Operations in a Storage Network
Storage System and Method for Flush Optimization
Handling Thermal Shutdown for Memory Devices
Patent:
10,013,194 →
Application:
15/611,958 →
Efficient Data Deduplication Leveraging Sequential Chunks or Auxiliary Databases
System and Method for Adaptive Command Fetch Aggregation
Selective Event Logging
Storage Device Operations Based on Bit Error Rate (Ber) Estimate
Dynamic Selection of Soft Decoding Information
Patent:
10,083,754 →
Application:
15/614,415 →
Hamming Distance Based Binary Representations Of Numbers
Patent:
9,912,352 →
Application:
15/614,914 →
Updating Read Voltages Triggered by the Rate of Temperature Change
Data Storage Device Configured to Perform a Non-Blocking Control Update Operation
Method and Data Storage Device Using Convolutional Low-Density Parity-Check Coding with a Long Page Write and a Short Page Read Granularity
Non-Volatile Storage Device with Adaptive Data Bus Inversion
Parameterized Iterative Message Passing Decoder
Temperature Variation Compensation
Method and System for User Experience Event Processing and Analysis
Storage System Having an Adaptive Workload-Based Command Processing Clock
Methods, Systems and Devices for Testing Circuit Modules Using a Microbackplane Interface
Efficient Data Management Through Compressed Data Interfaces
Data Storage Device Configured to Perform Operations Using a Wireless Interface
Data Recovery and Regeneration Using Parity Code
Cpu Error Remediation During Erasure Code Encoding
Determining Control States for Address Mapping in Non-Volatile Memories
Wear Leveling in Non-Volatile Memories
Wear Leveling in Non-Volatile Memories
3D Cross-Point Memory Manufacturing Process Having Limited Lithography Steps
Storage System with a Controller Having a Persistent Memory Interface to Local Memory
3D Cross-Point Memory Manufacturing Process Having Limited Lithography Steps
System and Method for Using Host Command Data Buffers as Extended Memory Device Volatile Memory
Patent:
10,114,586 →
Application:
15/630,438 →
Ecc Decoder with Selective Component Disabling Based on Decoding Message Resolution
Quality of Service Aware Storage Class Memory/Nand Flash Hybrid Solid State Drive
Storage System and Method for Improved Generation and Storage of Data Protection Information
Adaptive System for Optimization of Non-Volatile Storage Operational Parameters
Multi-Plane Memory Management
Non-Volatile Storage with Adaptive Redundancy
Dynamically Resizing Logical Storage Blocks
Block Management for Data Streams
Scaling Large Drives Using Enhanced Dram Ecc
Queue Depth Management for Host Systems Accessing a Peripheral Component Interconnect Express (Pcie) Device via a Pcie Switch
Program Temperature Aware Data Scrub
Patent:
10,026,483 →
Application:
15/636,023 →
Non-Volatile Storage Device System with Page Based Remapping
System and Method for Host System Memory Translation
Configurable Ecc Decoder
Virtual Root of Trust for Data Storage Device
Programmable Adapter Between Slow Peripherals and Network On-Chip Interfaces
Nesting and Shock Absorbing Package
Shroud for an Electronic Device
Identifying Memory Block Write Endurance Using Machine Learning
Read Disturb Compensation Using Weighted Programming Patterns
Distribution of Logical-to-Physical Address Entries Across Bank Groups
System and Method for Fast Execution of in-Capsule Commands
Efficient Management of Reference Blocks Used in Data Deduplication
Group Write Operations for a Data Storage Device
Methods, Systems and Devices for Restarting Data Processing Units
Storage System and Method for Die-Based Data Retention Recycling
Patent:
10,115,437 →
Application:
15/661,882 →
Non-Binary Encoding for Non-Volatile Memory
Method and System for Scanning for Erased Flash Memory Pages
Managing System Data for a Data Storage System
Read Level Tracking and Optimization
Planar Variable Resistance Memory
Component Placement Within a Solid State Drive
Systems, Methods, and Devices for Encoding and Decoding Data Using Multi-Layer Integrated Interleaved Codes
Non-Volatile Storage System with Compute Engine to Accelerate Big Data Applications
Non-volatile Memory Device With Secure Read
Geometry-Aware Command Scheduling
Non-Volatile Storage with Failure Prediction
Method for Maximizing Frequency While Checking Data Integrity on a Physical Interface Bus
Logical and Physical Address Field Size Reduction by Alignment-Constrained Writing Technique
Bottom Pinned Sot-Mram Bit Structure and Method of Fabrication
Method for Management Tables Recovery
Storage System and Method for Fast Lookup in a Table-Caching Database
File Consistency in Shared Storage Using Partial-Edit Files
Cloud-Based Management of Access to a Data Storage System on a Local Network
Using File System Extended Attributes to Recover Databases in Hierarchical File Systems
Clock Generator
Method and System for Input-Output Throttling to Improve Quality of Service in a Solid State Drive
Storage System and Method for Executing File-Based Firmware Commands and Collecting Response Data
Tilted Synthetic Antiferromagnet Polarizer/Reference Layer for Stt-Mram Bits
Method to Generate Pattern Data Over Garbage Data When Encryption Parameters Are Changed
System and Method to Enhance Solder Joint Reliability
Apparatus and Method for Low Power Low Latency High Capacity Storage Class Memory
Reactive Power Management for Non-Volatile Memory Controllers
Hidden Diagnostic Partition
Error Detection for Training Non-Volatile Memories
Storage Device Operations Using a Die Translation Table
Storage Protection Unit
Redundancy Coding Stripe Based On Coordinated Internal Address Scheme Across Multiple Devices
Redundancy Coding Stripe Based on Internal Addresses of Storage Devices
Multi-Level Cell Solid State Device and Method for Transferring Data Between a Host and the Multi-Level Cell Solid State Device
Error Reducing Matrix Generation
Hybrid Logical to Physical Address Translation for Non-Volatile Storage Devices with Integrated Compute Module
Non-Volatile Storage System with Integrated Compute Engine and Optimized Use of Local Fast Memory
Processing Data Access Requests from Multiple Interfaces for Data Storage Devices
Non-Volatile Memory with Dynamic Write Abort Detection and Recovery
Non-Volatile Memory with Regional and Inter-Region Wear Leveling
Erasure Correcting Coding Using Temporary Erasure Data
Methods and Apparatus for Variable Size Logical Page Management Based on Hot and Cold Data
Dynamic Management of Garbage Collection and Overprovisioning for Host Stream Storage
Identifying Disk Drives and Processing Data Access Requests
Uniform Performance Monitor for a Data Storage Device and Method of Operation
Dynamically Assigning Data Latches
Dynamic Multi-Stage Decoding
Lossless Synchronization Software Reset
Performance Based Memory Block Usage
Device-Based Anti-Malware
Wear Leveling in Non-Volatile Storage
Patent:
10,228,878 →
Application:
15/797,672 →
Adaptive Encoder/Decoder
Non-Volatile Memory with Backing Up of Programmed Data
Patent:
10,153,046 →
Application:
15/798,009 →
Non-Volatile Storage System That Reclaims Bad Blocks
Patent:
10,223,216 →
Application:
15/798,029 →
Activity Based Device Initiated State Transitions
Decryption and Variant Processing
Memory Station for Automatically Backing Up Data and Charging Mobile Devices
Non-Volatile Storage with Adaptive Command Prediction
System and Method for Flexible Management of Resources in an Nvme Virtualization Platform
Adaptive Device Quality of Service by Host Memory Buffer Range
System and Method for Qos Over Nvme Virtualization Platform Using Adaptive Command Fetching
Timestamp Suppression
Handling of Unaligned Sequential Writes
Raid Stripe Physical Placement
Managing Refresh Operations for a Memory Device
Adaptive Management of Intermediate Storage
Variable Length Cldpc Encoder and Method of Operation in an Autonomous Vehicle
Ecc and Raid-Type Decoding
System and Method for Time Stamp Synchronization
Three Terminal Sot Memory Cell with Anomalous Hall Effect
Non-Volatile Storage System with Read Calibration
Systems and Methods for Attaching Printed Circuit Board to Pallet
Clock Retiming Circuit
Single-Port Memory with Opportunistic Writes
Task Readiness for Queued Storage Tasks
Combined Control for Multi-Die Flash
Patent:
10,235,309 →
Application:
15/824,658 →
Library for Seamless Management of Storage Devices
Enhanced Erase Retry of Non-Volatile Storage Device
Streamed Program Commands with Periodic Garbage Collection
Dynamic Distributed Power Control Circuits
Patent:
10,228,746 →
Application:
15/832,528 →
Data Processing Offload Using In-Storage Code Execution
Data Storage Arrangement Partitionable Memory and Method to Accomplish Partition
Volatility Management for Non-Volatile Memory Device
Non-Volatile Memory with Adaptive Wear Leveling
Power Shaping and Peak Power Reduction by Data Transfer Throttling
Non-Volatile Memory and Method for Power Efficient Read or Verify Using Lockout Control
Storage of Neural Networks
Seed Generation
Optimized N-Stream Sequential Media Playback Caching Method and System
Semiconductor Device Including Optional Pad Interconnect
Patent:
10,249,587 →
Application:
15/843,951 →
Tilted Synthetic Antiferromagnet Polarizer/Reference Layer for Stt-Mram Bits
Method Using Logical Based Addressing for Latency Reduction
Dynamic Multi-Stage Decoding
Accessing Non-Volatile Memory Express Controller Memory Manager
Multi-Constraint Dynamic Resource Manager
Apparatus and Method of Detecting Potential Security Violations of Direct Access Non-Volatile Memory Device
Direct Host Access to Storage Device Memory Space
System and Method for Adjusting Read Levels in a Storage Device Based on Bias Functions
Location-Based Authentication and Monitoring for Data Storage Devices
Non-Volatile Memory with Dynamic Wear Leveling Group Configuration
Partial Program Operation of Memory Wordline
Read Threshold Adjustment Using Reference Data
Managing Flash Memory Read Operations
Integrated Usb Connector and Memory Device
Media Content Management Device
Search of Nas Data Through Association of Errors
Smart Device Security Compromised Warning Apparatus and Method
Code Rate Switching Mechanism for Flash Memory
Bi-Directional Rram Decoder-Driver
Storage System Comprising a Communications Port for Charging an Electronic Device
Memory Interface Initialization with Processor in Reset
Programming to a Correctable Amount of Errors
Thermal Management of Selector
Automatic Performance Tuning for Memory Arrangements
Memory Die Temperature Adjustment Based on a Power Condition
System and Method for Copy on Write on an Ssd
Scheduling Scheme(S) for a Multi-Die Storage Device
Implementing Deposition Growth Method for Magnetic Memory
Task Tail Abort for Queued Storage Tasks
Method and Apparatus for Selecting Power States in Storage Devices
Elimination of Crosstalk Effects in Non-Volatile Storage
Soft Information Module
Adaptive Power Balancing for Memory Device Operations
Reusing a Cell Block for Hybrid Dual Write
Cell Block Allocation for Hybrid Dual Write
Logical Grouping for Hybrid Dual Write
Data Availability During Memory Inaccessibility
Flash Fast Program Mode for High Definition Video Recording and High Resolution Camera Burst Mode Recording
Modularized Multi-Purpose Storage System
Methods and Apparatus for Implementing a Logical to Physical Address Mapping in a Solid State Drive
Completion Entry Throttling Using Data Storage Controller
Adaptive Bit-Flipping Decoder Based on Dynamic Error Information
Method and Apparatus for Programming Flash Based Storage Using Segmented Writes
Content-Aware Filter Options for Media Object Collections
Overlapping Write Schemes for Cross-Point Non-Volatile Memory Devices
Sram Bit-Flip Protection with Reduced Overhead
Data Shaping to Reduce Error Rates in Solid State Memory Devices
Methods and Apparatus for Controlling Flash Translation Layer Recycle from Host
Predicting Addresses in Non-Volatile Storage
Block Erase Schemes for Cross-Point Non-Volatile Memory Devices
Storage System and Method for Performing High-Speed Read and Write Operations
Storage System and Method for Generating a Reverse Map During a Background Operation and Storing It in a Host Memory Buffer
Probabilistic Neuron Circuits
Storage System and Method for Adaptive Scheduling of Background Operations
Non-Volatile Storage System with Host Side Command Injection
Energy Optimized Power State Declarations for Solid State Drives
Patent:
10,359,959 →
Application:
15/913,581 →
Dynamic Memory Compaction
Patent:
10,331,555 →
Application:
15/913,914 →
Adaptive Transaction Layer Packet for Latency Balancing
Storage Device and Method for Adaptive Sleep Mode Transitions
Adaptive Control of Host Queue Depth for Command Submission Throttling Using Data Storage Controller
Patent:
10,387,078 →
Application:
15/920,056 →
Adjustable Performance Parameters for Ssds
Storage System and Method for Determining Ecosystem Bottlenecks and Suggesting Improvements
Volatility Management for Memory Device
Storage Device with Multi-Die Management
Recovery Combining Hard Decoding, Soft Decoding and Artificial Codeword Generation
Encryption Detection and Backup Management
Dynamic Host Memory Allocation to a Memory Controller
Non-Volatile Storage with Wear-Adjusted Failure Prediction
Non-Volatile Memory System Including a Partial Decoder and Event Detector for Video Streams
Method to Unlock a Secure Digital Memory Device Locked in a Secure Digital Operational Mode
Validating Firmware for Data Storage Devices
Patent:
10,997,297 →
Application:
15/929,181 →
Determining Line Functionality According to Line Quality in Non-Volatile Storage
Log-Based Storage for Different Data Types in Non-Volatile Memory
Encoding and Decoding of Hamming Distance-Based Binary Representations of Numbers
On-Die Impedance Calibration
Patent:
10,224,928 →
Application:
15/934,379 →
Data Storage Device Read Threshold Adjustment According to Environmental Parameters
Patent:
10,379,739 →
Application:
15/934,816 →
Non-Volatile Storage System with Multi-Read Mode
Parity Generation Offload Using Peer-to-Peer Data Transfers in Data Storage System
Data Storage Drive Rebuild with Parity Generation Offload Using Peer-to-Peer Data Transfers
Symmetric and Continuous Media Stream from Multiple Sources
Adaptive Interleaving of Data Transfer Requests
Boundary Word Line Voltage Shift
Multi-Tier Memory Management
Patent:
10,360,155 →
Application:
15/946,387 →
Supervised Learning with Closed Loop Feedback to Improve Ioconsistency of Solid State Drives
Intelligent Sas Phy Connection Management
Suspending and Resuming a Read Operation for a Non-Volatile Memory
Method and System for Reading Data During Control Sync Operations
Mapping-Based Wear Leveling for Non-Volatile Memory
Program Verify Adaptation for Flash Memory
Multi-Stream Journaled Replay
Component-Efficient Cyclic-Redundancy-Check-Code-Computation Circuit
System and Method of Direct Write and Mapping of Data in a Non-Volatile Memory Having Multiple Sub-Drives
System and Method of Direct Write and Mapping of Data in a Non-Volatile Memory Having Multiple Sub-Drives
Secure Stream Buffer on Network Attached Storage
Parity Relocation for Reducing Temperature Throttling
Reducing Write-Backs to Memory by Controlling the Age of Cache Lines in Lower Level Cache
Advanced Flash Scan Algorithm
Block Reuse for Memory Operations
Method and Apparatus to Manipulate Customer Data Without Using the Host Interface
Seed Scrambling
Dynamic Calibration of Frequency and Power Storage Interface
Methods and Apparatus for Configuring Storage Tiers Within Ssds
Memory Failure Detection and Resource Allocation
Patent:
10,354,736 →
Application:
15/966,724 →
Method and Apparatus to Generate Zero Content Over Garbage Data When Encryption Parameters Are Changed
Intelligent Wide Port Phy Usage
Memory and Controller Mutual Secure Channel Association
Extended Controller Pre-Initialization Using Boot Partitions in Solid State Systems
Task Queues
Crash Log Storage and Retrieval Using Boot Partitions in Solid State Systems
Memory Die Temperature Adjustment Based on Aging Condition
Method for Maximizing Power Efficiency in Memory Interface Block
Solid State Drive Using Two-Level Indirection Architecture
System and Method for Direct Memory Access in a Flash Storage
Distributed Flash Interface Module Processing
Method and System for a Storage (Ssd) Drive-Level Failure and Health Prediction Leveraging Machine Learning on Internal Parametric Data
Data Storage System for Improving Data Throughput and Decode Capabilities
Systolic Neural Network Engine Capable of Forward Propagation
Systolic Neural Network Engine Capable of Backpropagation
Systolic Neural Network Engine with Crossover Connection Optimization
Convolution Engines for Systolic Neural Network Processor
Systolic Neural Network Processor with Feedback Control
Multi-Core Systolic Processor System for Neural Network Processing
Priority Addresses for Storage Cache Management
Locality Grouping During Garbage Collection of a Storage Device
Locality Grouping During Garbage Collection with Flush of Buffered Write Data Upon Completion of Garbage Collection Operation
Hierarchical Clock Scaling in a Data Storage Controller
Failure Prediction by Cell Probing
Patent:
10,410,732 →
Application:
15/985,588 →
Multiple Sets of Trim Parameters
Partial Reset of a Memory Controller
Storage System and Method for Soft-Decision-Based Command Execution to Enhance Random Write Performance
Non-Volatile Storage System with Command Replay
Efficiently and Dynamically Sized Reverse Map to Handle Variable Size Data
Memory Efficient Persistent Key-Value Store for Non-Volatile Memories
Processor with Processor Memory Pairs for Improved Process Switching and Methods Thereof
Temperature Variation Compensation
Memory Health Monitoring
Method and Apparatus for Classifying and Buffering Write Commands
Trie Search Engine
Temperature Variation Compensation
On-Chip Copy with Data Folding in Three-Dimensional Non-Volatile Memory Array
Power-Safe Data Management System
Wear Leveling in Solid State Devices
System and Method for Time Stamp Synchronization
Enhanced Read-Ahead Capability for Storage Devices
Balanced Caching Between a Cache and a Non-Volatile Memory Based on Rates Corresponding to the Cache and the Non-Volatile Memory
Optimized Garbage Collection for Solid-State Storage Devices
Storage Drive and Method of Executing a Compare Command
Memory Device with Adaptive Descrambling
Storage System and Method for Efficient Pipeline Gap Utilization for Background Operations
Unitary Molded Usb Device
Power Adapter with Protection Circuitry
Multi-Level Phase Change Device
Resistive Memory Device by Substrate Reduction
Handling Thermal Shutdown for Memory Devices
Removal Delay Feature for Removably Connected Devices
Patent:
10,361,511 →
Application:
16/020,456 →
Relaxed Erase Parameters for Block Erasures in Non-Volatile Storage Media
Non-Volatile Storage System with Dynamic Allocation of Applications to Memory Based on Usage Monitoring
Error Correction Decoding with Redundancy Data
Bifurcated Memory Die Module Semiconductor Device
Manufacturing Process for Separating Logic and Memory Array
Semiconductor Device Including Through-Package Debug Features
Storage System and Method for Namespace Reservation in a Multi-Queue Single-Controller Environment
Error Correction Decoding Augmented with Error Tracking
Noise Injection Training for Memory-Based Learning
Grown Defect Detection and Mitigation Using Ecc in Memory Systems
Collision Detection for Slave Storage Devices
System and Method for Dynamic Allocation to a Host of Memory Device Controller Memory Resources
System and Method for Predictive Read of Random Data
System and Method for Prediction of Read Commands to Non-Sequential Data
Quality of Service Based Arbitrations Optimized for Enterprise Solid State Drives
Controlling Cached/Non-Cached Memory Access Decisions Based on Memory Access Queue Fill Levels
Buffering Storage Device Data in a Host Memory Buffer
Method and Apparatus for Adaptive Data Retention Management in Non-Volatile Memory
Methods and Systems for a Portable Data Locker
Incremental Snapshot Based Technique on Paged Translation Systems
Reporting Available Physical Storage Space of Non-Volatile Memory Array
Method and System for Improving Open Block Data Reliability
Speculative Pre-Fetching of Flash Translation Layer Tables for Use with Solid State Systems
Automated Voltage and Timing Margin Measurement for Nand Flash Interface
System and Method for Augmentation of Reset Recovery Operation Timing
Debug Data Recovery After Pli Event
Self-Trimming of Data Stored in Non-Volatile Memory Using Data Storage Controller
Unified Paging Scheme for Dense and Sparse Translation Tables on Flash Storage Systems
Direct Measurement Delay Calibration Method and Apparatus
Patent:
10,411,719 →
Application:
16/051,374 →
Adjustable Read Retry Order Based on Decoding Success Trend
Combined Data and Control for Multi-Die Flash
Hardware Assisted Firmware Download Syncing
Power Safe Offline Download
Solid State Device with Distributed Bit Buckets
Methods and Apparatus for Mitigating Temperature Increases in a Solid State Device (Ssd)
Methods and Apparatus for Host Register Access for Data Storage Controllers for Ongoing Standards Compliance
Placement of Host Data Based on Data Characteristics
System and Method for Storage Device Management
Logical and Physical Address Field Size Reduction by Alignment-Constrained Writing Technique
Diffused Resistive Memory Cell with Buried Active Zone
Soft-Decision Input Generation for Data Storage Systems
Patent:
10,635,524 →
Application:
16/112,429 →
Providing Digital Video Assets with Multiple Age Rating Levels
Characterizing and Operating a Non-Volatile Memory Device
Methods and Systems for Privileged Execution Support for File System Commands on a Storage Device
Pre-Program Read to Counter Wordline Failures
Data Storage Systems and Methods for Improved Recovery After a Write Abort Event
Ssd Firmware Download Dual Boot
In-Field Adaptive Drive Recovery
Expandable Memory for Use with Solid State Systems and Devices
Content Aware Decoding Method and System
Logical Block Addressing Rangecollision Crawler
Universal Serial Bus Voltage Reducing Adaptor
Adjustment of Storage Device Parameters Based on Workload Characteristics
Read Commands Scheduling Method in Storage Device
Error Recovery of Cross-Die Logical Pages in a Solid State Device
Solid State Device with Fast Boot After Ungraceful Shutdown
Self-Prioritizing Adaptive Retry Threshold Adjustment
Multi-Sensing Scan for Cross-Temperature Mitigation
Efficient Power Management Stand-by Modes for Multiple Dies in a Storage Device
Adaptive Transaction Layer Packet for Latency Balancing
Decoding Data Using Decoders and Neural Networks
Recency Based Victim Block Selection for Garbage Collection in a Solid State Device (Ssd)
Data Storage Device Equipped to Reduce Page Faults in Host Device
Semiconductor Device with Die-Skipping Wire Bonds
Data Storage Systems and Methods for Improved Data Relocation Based on Read-Level Voltages Associated with Error Recovery
Storage System and Method for Die-Based Data Retention Recycling
Non-Volatile Storage System with Command Response Piggybacking
Dedicated Termination Dies for Memory Systems
Series Resistance in Transmission Lines for Die-to-Die Communication
Active Low-Power Termination
Patent:
10,461,965 →
Application:
16/146,697 →
Electrostatic Discharge Protection Circuit and Design
Method for Fast Boot Read
System and Method for Using Host Command Data Buffers as Extended Memory Device Volatile Memory
Wear Leveling with Wear-Based Attack Detection for Non-Volatile Memory
System and Method for Performance-Based Multiple Namespace Resource Allocation in a Memory
Systems and Methods for Offloading Processing from a Host to Storage Processing Units Using an Interconnect Network
Multi-Dimensional Quasi-Cyclic (Qc) Low-Density Parity-Check (Ldpc) Code Constructions
Address Range Mapping for Storage Devices
System and Method to Improve Input Output Command Latency by Dynamic Size Logical to Physical Caching
Write Level Optimization for Non-Volatile Memory
Zoned Block Command to Stream Command Translator
Storing Deep Neural Network Weights in Non-Volatile Storage Systems Using Vertical Error Correction Codes
Methods and Apparatus for Workload Based Dynamic Cache Control in Ssd
Devices and Methods for Decoupling of Physical Layer
Methods and Systems for Implementing Redundancy in Memory Controllers
Data Storage Device with Deadlock Recovery Capabilities
Bounded Latency and Command Non Service Methods and Apparatus
Ethernet in Data Storage Device
Storing Neural Networks and Weights for Neural Networks
Method for Enhancing Ssd Endurance by Utilizing Host Dram
Decentralized Data Processing Architecture
Electrostatic Discharge Protection Circuit
Bandwidth Limiting in Solid State Drives
Solid State Device with Improved Sustained Data Writing Speed
Methods and Systems for Object Level De-Duplication for Solid State Devices
Data Access in Data Storage Device Including Storage Class Memory
Symbol-Based Variable Node Updates for Binary Ldpc Codes
Storage System and Method for Stream Management in a Multi-Host Virtualized Storage System
Extending the Error Correction Capability of a Device Using a Neural Network
Dual Media Packaging Targeted for Ssd Usage
Non-Volatile Memory Die with Deep Learning Neural Network
Non-Volatile Memory Die with Deep Learning Neural Network
Transistor Threshold Voltage Maintenance in 3D Memory
Flash Storage Device with Data Integrity Protection
Enhancing the Effectiveness of Read Scan Performance and Reliability for Non-Volatile Memory
Multi-Level Cell Programming Using Optimized Multiphase Mapping with Balanced Gray Code
Multi-State Programming for Memory Devices
Mapping for Multi-State Programming of Memory Devices
Data Storage Systems and Methods for Autonomously Adapting Data Storage System Performance, Capacity and/or Operational Requirements
Apparatus and Methods for Merging Post-Write Read and Select Gate Maintenance Operations
Non-Volatile Storage System with Reduced Program Transfers
Adaptive-Feedback-Based Read-Look-Ahead Management System and Method
System and Method for Prediction of Multiple Read Commands Directed to Non-Sequential Data
Performance of a Read in a Memory System
Workload Based Dynamic Erase Suspend Adaptation
Patent:
10,643,711 →
Application:
16/228,599 →
On-Chip Non-Volatile Memory (Nvm) Search
Configurable Neural Network Engine of Tensor Arrays and Memory Cells
Reconfigurable Systolic Neural Network Engine
Adjusting Enhancement Coefficients for Neural Network Engine
Configurable Neural Network Engine for Convolutional Filter Sizes
Incomplete Write Group Journal
Method of Identifying and Preparing a Key Block in a Flash Memory System and Memory Controller Therefor
Measurement, Calibration and Tuning of Memory Bus Duty Cycle
Patent:
10,622,982 →
Application:
16/244,924 →
Tiered Storage Data Evacuation Within Solid State Devices
Data Storage Systems and Methods for Optimized Scheduling of Background Management Operations
Fine Granularity Translation Layer for Data Storage Devices
Container Key Value Store for Data Storage Devices
Non-Volatile Storage System with Rapid Recovery from Ungraceful Shutdown
System and Method for Storage System Property Deviation
Non-Volatile Storage System That Reclaims Bad Blocks
Memory Device with Enhanced Error Correction
Method and System for Improving Performance of a Storage Device Using Asynchronous Independent Plane Read Functionality
Patent:
10,685,722 →
Application:
16/256,010 →
Balancing the Block Wearing Leveling for Optimum Ssd Endurance
High Voltage Protection for High-Speed Data Interface
Logical to Physical Mapping Management Using Low-Latency Non-Volatile Memory
Post Write Erase Conditioning
Flash Translation Layer Table for Unaligned Host Writes
System and Method for Prediction of Random Read Commands in Virtualized Multi-Queue Memory Systems
System and Method for Configuring a Storage Device Based on Prediction of Host Source
Data Storage Systems and Methods for Self Adaptive Chip-Enable Setup Time
Systems and Methods to Optimally Select Metablocks
Non-Volatile Memory with Replay Protected Memory Block Having Dual Key
Thread-Aware Controller
Systems and Methods for Heterogeneous Address Space Allocation
Systems and Methods for Wireless Charging and Wired Data Transfer
Super-Sparse Image Compression Using Cross-Bar Non-Volatile Memory Device
Semiconductor Device Including Reinforced Corner Supports
Semiconductor Device Including Through Vias in Molded Columns
Data Storage Devices and Connectors for Same
Operating Parameters for Flash Memory Devices
System for Generating Random Noise with a Magnetic Device
Patent:
10,719,298 →
Application:
16/284,613 →
3-Dimensional Nand Flash Layer Variation Aware Ssd Raid
Techniques for Performing a Non-Blocking Control Sync Operation
Tsv Semiconductor Device Including Two-Dimensional Shift
Memory Die Layouts for Failure Protection in Ssds
System and Method for Scaling a Historical Pattern Matching Data Structure in a Memory Device
Patent:
10,719,445 →
Application:
16/288,784 →
System and Method for Chain Prediction of Multiple Read Commands
Patent:
10,725,781 →
Application:
16/289,042 →
Systems and Methods to Wake Up Memory Array
Failure Mode Study Based Error Correction
Vertical Surface Mount Type C Usb Connector
Patent:
10,733,136 →
Application:
16/290,116 →
Data Transfer Command Latency of a Host Device
Patent:
10,642,764 →
Application:
16/290,705 →
Retention-Aware Data Tiering Algorithm for Hybrid Storage Arrays
Burst Mode Operation Conditioning for a Memory Device
Multi-Phased Programming with Balanced Gray Coding
Leaky Memory Hole Repair at Fabrication Joint
Executable Memory Cells
Read Level Tracking and Optimization
Executable Memory Cell
Shifting Architecture for Data Reuse in a Neural Network
Punctured Bit Estimation and Bit Error Rate Estimation
Solid State Drive Latency Estimation Interface for Host Performance Tuning
Storage System and Method for Early Host Command Fetching In a Low Queue Depth Environment
Enhanced Memory Device Architecture for Machine Learning
Enhanced Storage Device Memory Architecture for Machine Learning
Optimized Handling of Multiple Copies in Storage Management
Single Page Read Level Tracking by Bit Error Rate Analysis
Secure Storage Using a Removable Bridge
Secure Firmware Booting
Storage System and Method for Thin Provisioning
Selective Deduplication Based on Data Storage Device Controller Status and Media Characteristics
Host-Trusted Module in Data Storage Device
Storage Device with a Callback Response
Neural Networks Using Data Processing Units
Multi-Tier Scheme for Logical Storage Management
Memory Card Pad Layout Supporting Multiple Communication Protocols
System Level Data-Loss Protection Using Storage Device Local Buffers
Preserving Data Upon a Power Shutdown
Sharing Groups for Capturing Digital Media
Cam Storage Schemes and Cam Read Operations for Detecting Matching Keys with Bit Errors
Physical Secure Erase of Solid State Drives
Fast Storage Class Memory Using Write Once Memory Coding
Semiconductor Device Including Dummy Pull-Down Wire Bonds
Systems and Methods for Finding a Last Good Page in Nand Open Block
Spin-Orbit-Torque Magnetoresistive Memory Cell with Integrated Selector Elements and Method of Making the Same
Non-Volatile Storage System with Hybrid Command
Systems and Methods for Wireless Charging and Wireless Data Transfer
Systems and Methods for Wireless Charging and Wireless Data Transfer for Multiple Devices
Decoding with Data Mapping Methods and Systems
Storage System and Method for Preventing Head-of-Line Blocking in a Completion Path
Patent:
10,740,243 →
Application:
16/410,116 →
Detecting a Faulty Memory Block
Patent:
10,770,158 →
Application:
16/412,657 →
Enhanced Solid-State Drive Write Performance With Background Erase
Patent:
10,658,045 →
Application:
16/412,859 →
Memory Circuit for Halting a Program Counter While Fetching an Instruction Sequence from Memory
Dynamic Read Based on Read Statistics
Optimized Neural Network Data Organization
Virtual Physical Erase of a Memory of a Data Storage Device
Reducing Post-Read Disturb in a Nonvolatile Memory Device
Sub Block Mode Read Scrub Design for Non-Volatile Memory
Patent:
10,734,079 →
Application:
16/415,923 →
System and Method for Performing Discriminative Predictive Read
Hot Spot Cooling For Data Storage System
Metadata-Based Operations for Use with Solid State Devices
Host and Method for Storage System Calibration
Storage System and Method for Storage System Calibration
Storage Device with Predictor Engine of Host Turnaround Time
Patent:
10,761,999 →
Application:
16/427,076 →
Scheme to Reduce Read Disturb for High Read Intensive Blocks in Non-Volatile Memory
Memory Device with Enhanced Error Correction via Data Rearrangement, Data Partitioning, and Content Aware Decoding
Enabling High Speed Command Address Interface for Random Read
Offloading File-Indexing to Memory Card Firmware
Adaptive Usage of Irregular Code Schemas Based on Specific System Level Triggers and Policies
Socket Interconnector with Compressible Ball Contacts for High Pad Count Memory Cards
Multi-Level Loop Cut Process for a Three-Dimensional Memory Device Using Pitch-Doubled Metal Lines
Execution Condition Embedded in a Command or a Request to Storage Device
Patent:
11,275,527 →
Application:
16/438,381 →
Socket Interconnector for High Pad Count Memory Cards
Using Interleaved Writes to Separate Die Planes
Three-Dimensional Phase Change Memory Device Including Vertically Constricted Current Paths and Methods of Manufacturing the Same
Three-Dimensional Memory Device Including Laterally Constricted Current Paths and Methods of Manufacturing the Same
POWER TARGET CALIBRATION FOR CONTROLLING DRIVE-TO-DRIVE PERFORMANCE VARIATIONS IN SOLID STATE DRIVES (SSDs)
Soft Erase and Programming of Nonvolatile Memory
Memory Device Containing Ovonic Threshold Switch Material Thermal Isolation and Method of Making the Same
Semiconductor Device with Die Bumps Aligned with Substrate Balls
Adaptive Read Trim for Second Read Data Retention
Storage System and Method for Enabling Host-Driven Regional Performance in Memory
Storage System and Method for Memory Backlog Hinting for Variable Capacity
Dynamic Switching for Improved Power Utilization
Multi-Stream Non-Volatile Storage System
Intelligent Power Saving Mode for Solid State Drive (Ssd) Systems
Non-Volatile Memory Die with on-Chip Data Augmentation Components for Use with Machine Learning
Partial Xor Protection
Method to Switch Between Traditional Ssd and Open-Channel Ssd Without Data Loss
Yield Improvement Through Block Budget Optimization by Using a Transient Pool of Multi-Level Blocks
Updating Mapping Information During Synchronization of Memory Device
Host Emulator
Flash Memory Polling
Translucid Access to Storage Devices
Optimizing Data Storage Device Operation by Grouping Logical Block Addresses and/or Physical Block Addresses Using Hints
Non-Volatile Storage System with Fast Slc Operation
Adaptable Logical to Physical Tables for Multiple Sector Pattern Support
Sockets for Removable Data Storage Devices
Hardware Accelerated Discretized Neural Network
Delayed Write Failure Logging
Non-Volatile Storage System with Data Shaping Memory Partitions
File System Metadata Decoding for Optimizing Flash Translation Layer Operations
Energy Optimized Power State Declarations for Solid State Drives
Address Translation for Storage Device
Extensible Storage System and Method
Data Driven Icad Graph Generation
Power Shaping and Peak Power Reduction by Data Transfer Throttling
Solid State Drive Cache Eviction Policy by an Unsupervised Reinforcement Learning Scheme
Automatically Adapt User Interface Color Scheme for Digital Images and Video
Multi-Level Phase Change Memory Cells and Method of Making the Same
Method and System for Address Table Eviction Management
Neural Network Engine Utilizing a Serial Bus
System and Method for Decoding Iterations and Dynamic Scaling
Storage System and Method for Hit-Rate-Score-Based Selective Prediction of Future Random Read Commands
Non-Volatile Memory Data Write Management
Two-Dimensional Scalable Versatile Storage Format For Data Storage Devices
Write Operation Verification Method and Apparatus
Recovery of Validity Data for a Data Storage System
Geometry-Aware Command Scheduling
Invalidation Data Area for Cache
System and Method for Adaptive Early Completion Posting Using Controller Memory Buffer
System and Method to Enhance Solder Joint Reliability
Hardware-Assisted Multi-Table Database with Shared Memory Footprint
Method and System for Identifying Erased Memory Areas
Error Correction Scheme in Flash Memory
Systems and Methods for Managing Physical-to-Logical Address Information
Multidimensional Pseudorandom Binary Sequence Analysis for a Memory Device
Management Operations in Predictable Latency Mode
Data Storage Devices and Connectors for Same
Patent:
10,716,225 →
Application:
16/457,134 →
Systems And Methods For Evaluating Integrity Of Adjacent Sub Blocks Of Data Storage Apparatuses
Integrated Power and Thermal Management in Non-Volatile Memory
Log-Based Storage for Different Data Types in Non-Volatile Memory
Perpendicular Sot Mram
Open Channel Vector Command Execution
Perpendicular Spin Transfer Torque Mram Memory Cell with in-Stack Thermal Barriers
Heat Assisted Perpendicular Spin Transfer Torque Mram Memory Cell
Patent:
10,777,248 →
Application:
16/459,389 →
Task Queues
Enabling Secondary Scratchpad Cache With Solid-State Devices For Low Cost Hosts
Patent:
10,732,878 →
Application:
16/510,550 →
Automatic Host Buffer Pointer Pattern Detection
Method for Delaying Fundamental Reset in Power Loss Protection (PLP) Enabled Devices
Dynamic and Adaptive Data Read Request Scheduling
System Data Storage Mechanism Providing Coherency and Segmented Data Loading
Managing Data for a Data Storage System
Generalized Verification Scheme For Safe Metadata Modification
Rolling XOR Protection in Efficient Pipeline
Wafer Testing System Including a Wafer-Flattening Multi-Zone Vacuum Chuck and Method for Operating the Same
Apparatus for Obsolete Mapping Counting in NAND-based Storage Devices
System and Method for Direct Memory Access in a Flash Storage
System and Method of Direct Write and Mapping of Data in a Non-Volatile Memory Having Multiple Sub-Drives
Search Time Optimization in Solid-State Devices
Spin-Transfer Torque Magnetoresistive Memory Device with a Free Layer Stack Including Multiple Spacers and Methods of Making the Same
Computational Resource Allocation in Ensemble Machine Learning Systems
Managing Phys of a Data Storage Target Device
Non-Volatile Storage System with Filtering of Data Samples for a Monitored Operational Statistic
Storage System and Method for Validation of Hints Prior to Garbage Collection
Secure Stream Buffer on Network Attached Storage
Memory Card System with Improved Password Reset Method
Performance of Non Data Word Line Maintenance in Sub Block Mode
Patent:
10,832,790 →
Application:
16/584,684 →
Systems and Methods for Data Storage in a Memory System
Uncorrectable Error Correction Code (Uecc) Recovery Time Improvement
Method and System For Managing Memory Device
Run-Time Memory Device Failure Detection Enhancement
System and Method of Data Writes and Mapping of Data for Multiple Sub-Drives
Non-Volatile Memory with Selective Interleaved Coding Based on Block Reliability
Patent:
10,871,910 →
Application:
16/586,895 →
Write Efficiency in Magneto-Resistive Random Access Memories
Granular Refresh Rate Control for Memory Devices Based on Bit Position
Retrieval of Network Site Data with Data Storage Device Utilizing User Authentication
Method Using Logical Based Addressing for Latency Reduction
Accessing Non-Volatile Memory Express Controller Memory Manager
Interleaved Host Reset and Next Re-Initialization Operations
Patent:
10,860,333 →
Application:
16/600,816 →
Efficiently Identifying Command Readiness Based On System State And Data Spread In Multi Queue Depth Environment
Extending Operating Temperature of Storage Device
Magnetoresistive Random Access Memory Containing Multilayer Synthetic Antiferromagnetic Structure and Method of Making Thereof
Partitioned Non-Volatile Memory Express Protocol for Controller Memory Buffer
Cross-Point Spin-Transfer Torque Magnetoresistive Memory Array and Method of Making the Same
Method and System for Visualizing Sleep Mode Inner State Processing
Encoding Digital Videos Using Controllers of Data Storage Devices
Iterative Decoder Performance Prediction Using Machine Learning
Storage Class Memory Access
Electric Field Controllable Spin Filter Tunnel Junction Magnetoresistive Memory Devices and Methods of Making the Same
Electric Field Controllable Spin Filter Tunnel Junction Magnetoresistive Memory Devices and Methods of Making the Same
Patent:
10,964,748 →
Application:
16/686,917 →
Pattern Tracking For Efficiently Predicting Control Pages
Volatility Management for Non-Volatile Memory Device
Stacked Die Package with Curved Spacer
Magnetoresistive Memory Device Including a High Dielectric Constant Capping Layer and Methods of Making the Same
Patent:
10,991,407 →
Application:
16/692,903 →
Magnetoresistive Memory Device Including a High Dielectric Constant Capping Layer and Methods of Making the Same
Magnetoresistive Memory Device Including a High Dielectric Constant Capping Layer and Methods of Making the Same
Error Recovery Handling
System and Method for Adaptive Command Fetch Aggregation
Priority-Based Data Movement
Non-Volatile Storage System with Adaptive Command Processing
Pad Indication for Device Capability
Non-Sequential Zoned Namespaces
Zone Formation for Zoned Namespaces
Wire Bond Pad Design for Compact Stacked-Die Package
Non-Volatile Memory with on-Chip Principal Component Analysis for Generating Low Dimensional Outputs for Machine Learning
Unlocking a Data Storage Device
Multi-Device Unlocking of a Data Storage Device
Storage System and Method for Reducing Read-Retry Duration
Storage System and Method for Caching a Single Mapping Entry for a Random Read Command
Storage System and Method for Video Frame Segregation to Optimize Storage
Patent:
10,841,645 →
Application:
16/708,091 →
Storage System and Sorting-Based Method for Random Read Command Prediction in a Multi-Queue System
Skip Coding for Fractional Bit-Per-Cell Nand Memories
Patent:
10,964,390 →
Application:
16/709,338 →
Different Word Line Programming Orders in Non-Volatile Memory for Error Recovery
Patent:
10,943,662 →
Application:
16/709,709 →
System and Method for a Storage Controller Having a Persistent Memory Interface to Local Memory
Zoned Namespace Management of Non-Volatile Storage Devices
Application:
16/712,659 →
Publication:
US 2021/0182166
Error Recovery from Submission Queue Fetching Errors
Storage System and Method for User-Defined Data Archiving
Transformation of Binary Data to Non-Binary Data For Storage in Non-Volatile Memory
Data Storage System and Method for Decoding Data based on Extrapolated Flipped-Bit Data
Storage System and Method for Improving Utilization of a Communication Channel between a Host and the Storage System
Storage Controller Having Data Augmentation Components for Use with Non-Volatile Memory Die
Decoding Optimization for Channel Mismatch
Host and Method for Interleaving Data in a Storage System for Enhanced Quality of Service
Storage System and Method for Interleaving Data for Enhanced Quality of Service
Measuring Performance Metrics for Data Storage Devices
Manufacturing Process for Separating Logic and Memory Array
Soft Bit Read Mode Selection for Non-Volatile Memory
Data Storage Device with Dynamic Stripe Length Manager
Data Storage Device and Method for Memory Operation and Iterative Polling
Data Storage System and Method Based on Data Temperature
Flexible Accelerator for Sparse Tensors (Fast) in Machine Learning
Zoned Namespaces in Solid-State Drives
Storage System and Method for Secure Host Controller Memory Buffer Access
Automatic Data Backup and Charging of Mobile Devices
Debug Systems for Deterministic Validation of Data Storage Devices
Storage System and Method for Enabling a Direct Accessible Boot Block in a Memory Die
System and Method for Reduced Latency of Read-Modify-Write Operations
Dynamic Predictive Latency Attributes
Apparatus and Method for Handling Temperature Dependent Failures in a Memory Device
Multi-Role Unlocking of a Data Storage Device
Recovery Key for Unlocking a Data Storage Device
Remote Grant of Access to Locked Data Storage Device
Secure Logging of Data Storage Device Events
Efficient Data Management Through Compressed Data Interfaces
Data Processing Offload Using In-Storage Code Execution
Initializing a Data Storage Device with a Manager Device
Enrolment of Pre-Authorized Device
Dummy Host Command Generation For Supporting Higher Maximum Data Transfer Sizes (MDTS)
Method and System for Host-Assisted Data Recovery Assurance for Data Center Storage Device Architectures
Queue Depth Management for Host Systems Accessing a Peripheral Component Interconnect Express (Pcie) Device via a Pcie Switch
Method and Device for Simultaneously Decoding Data in Parallel to Improve Quality of Service
Content Aware Bit Flipping Decoder
Post Write Erase Conditioning
Managing Phys of a Data Storage Target Device Backgroung of the Disclosure
System and Method for Copy on Write on an Ssd
Calculating the Optimal Number of Lbns to Prefetch Per Cpu
Storage Device Operations Using A Die Translation Table
Multi-Tier Scheme for Logical Storage Management
Dynamic Multi-Stage Decoding
Temperature Variation Compensation
Calibrating Optimal Read Levels
Storage System and Method for Maintaining Uniform Hot Count Distribution Using Smart Stream Block Exchange
Using File System Extended Attributes to Update Databases in Hierarchical File Systems
Access Control in CMB/PMR Virtualization Environment
NVMe SGL Bit Bucket Transfers
Storage System and Method for Host Memory Access
Storage System and Method for Boundary Wordline Data Retention Handling
Magnetic Device Including Multiferroic Regions and Methods of Forming the Same
Storage System and Method for Automatic Data Phasing
Storage System and Method for Optimized Surveillance Search
Dual SLC/QLC Programming and Resource Releasing
Training Data Sample Selection for Use with Non-Volatile Memory and Machine Learning Processor
NAND Dropped Command Detection and Recovery
Thermal Relief for Through-Hole and Surface Mounting
Restricting Access to a Data Storage System on a Local Network
Method and System for Address Table Cache Management Based on Correlation Metric of First Logical Address and Second Logical Address, Wherein the Correlation Metric Is Incremented and Decremented Based on Receive Order of the First Logical Address and the Second Logical Address
Patent:
10,997,080 →
Application:
16/788,117 →
Storage Device With Increased Endurance
Patent:
11,061,768 →
Application:
16/791,560 →
Dynamically Adjust Data Transfer Speed for Non-Volatile Memory Die Interfaces
Patent:
10,971,215 →
Application:
16/798,590 →
Variable Read Scan for Solid-State Storage Device Quality of Service
Data Storage Device Adaptor with Securement Mechanism
Data Storage With Improved Write Performance For Preferred User Data
Patent:
10,923,178 →
Application:
16/802,638 →
Embedded PHY (EPHY) IP Core for FPGA
Data Storage With Improved Suspend Resume Performance
Data Storage Device With Improved Interface Transmitter Training
Cycle Borrowing Counter
Semiconductor Device with Top Die Positioned to Reduce Die Cracking
Semiconductor Device Including Magnetic Hold-Down Layer
Semiconductor Device Including Contact Fingers on Opposed Surfaces
Storage System and Method for Implementing an Encoder, Decoder, and/or Buffer Using a Field Programmable Gate Array
Snapshot Management in Partitioned Storage
Semiconductor Device Including High Speed Heterogeneous Integrated Controller and Cache
Semiconductor Die and Semiconductor Package
Storage System and Method for Improved Playback Analysis
Combined QLC Programming Method
High Capacity Semiconductor Device Including Bifurcated Memory Module
Multi-Module Integrated Interposer and Semiconductor Device Formed Therefrom
Semiconductor Device Including Vertically Stacked Semiconductor Dies
Methods and Systems for Implementing Redundancy in Memory Controllers
Measurement, Calibration and Tuning of Memory Bus Duty Cycle
Aperture Structure on Semiconductor Component Backside to Alleviate Delamination in Stacked Packaging
Extensible Storage System And Method
System and Method to Enhance Reliability in Connection with Arrangements Including Circuits
Soft-Decision Input Generation for Data Storage Systems
Entropy Driven Endurance For Normalized Quality Of Service
Patent:
11,082,168 →
Application:
16/823,714 →
Systems and Methods for Multi-Zone Data Tiering for Endurance Extension in Solid State Drives
Dynamic Multi-Stage Decoding
Multi-Stream Journaled Replay
Adjustable Read Retry Order Based on Decoding Success Trend
Distribution of Logical-to-Physical Address Entries Across Bank Groups
Voltage-Controlled Interlayer Exchange Coupling Magnetoresistive Memory Device and Method of Operating Thereof
Systems and Methods for Queuing Device Management Configuration Requests
Code Rate Switching Mechanism for Data Storage System
Power Management for Data Storage Devices Implementing Non-Volatile Memory (Nvm) Sets
Patent:
11,061,619 →
Application:
16/827,548 →
Adjustable Performance Parameters for Ssds
Context-Aware Dynamic Command Scheduling For A Data Storage System
Data Storage Device, Method and System, and Control of Data Storage Device Based on Writing Operations and Lifetime
Wear Leveling in Solid State Devices
Dynamic Allocation Of Sub Blocks
Flexible Accelerator for Sparse Tensors in Convolutional Neural Networks
Flexible Accelerator for Sparse Tensors in Convolutional Neural Networks
Non-Volatile Memory Array with Write Failure Protection for Multi-Level Cell (Mlc) Storage Elements Using Coupled Writes
Intelligent Sas Phy Connection Management
Bandwidth Limiting in Solid State Drives
Temperature Variation Compensation
Separate Storage and Control of Static and Dynamic Neural Network Data Within a Non-Volatile Memory Array
Dynamic Zns Open Zone Active Limit
Command Optimization Through Intelligent Threshold Detection
Snapback Electrostatic Discharge Protection For Electronic Circuits
Patent:
11,056,880 →
Application:
16/835,837 →
Dual-Connector Storage System and Method for Simultaneously Providing Power and Memory Access to a Computing Device
Flow Control of Large Sequential Host Read Commands Based on a Queue Threshold
Boosting Reads of Chunks of Data
Advanced CE encoding for bus multiplexer grid for SSD
Smart Erase Verify Test to Detect Slow-Erasing Blocks of Memory Cells
Read Modify Write Optimization for Video Performance
Advanced File Recovery Method For Flash Memory
Zone-append command scheduling based on zone state
Weighting Of Read Commands to Zones In Storage Devices
Adapting Transmitter Training Behavior Based Upon Assumed Identity Of Training Partner
Storage System and Method for Multiprotocol Handling
Dynamic Memory Controller and Method for Use Therewith
Tunneling Metamagnetic Resistance Memory Device and Methods of Operating the Same
Keeping Zones Open With Intermediate Padding
Tunneling Metamagnetic Resistance Memory Device and Methods of Operating the Same
Variable Power Mode Inferencing
Storage Device Parameter Monitoring for Load Balancing
Low Resistance Monosilicide Electrode for Phase Change Memory and Methods of Making the Same
Patent:
11,114,157 →
Application:
16/857,053 →
Mechanism to Improve Driver Capability With Fine Tuned Calibration Resistor
Patent:
11,024,353 →
Application:
16/858,223 →
Storage Devices Having Minimum Write Sizes Of Data
Storage Devices Having Minimum Write Sizes Of Data
Data Parking for SSDs with Zones
Data Parking for SSDs with Streams
Application:
16/858,350 →
Publication:
US 2021/0333996
Storage Devices Hiding Parity Swapping Behavior
Patent:
11,055,176 →
Application:
16/858,356 →
Storage Devices Hiding Parity Swapping Behavior
Weighted Read Commands And Open Block Timer For Storage Devices
System for Accelerated Training of Bit Output Timings
Zone-based device with control level selected by the host
SSD Address Table Cache Management based on Probability Distribution
Condensing Logical to Physical Table Pointers in SSDs Utilizing Zoned Namespaces
Pre-Program Read to Counter Wordline Failures
Data Storage Systems and Methods for Self Adaptive Chip-Enable Setup Time
Method and System for Improving Performance of a Storage Device Using Asynchronous Independent Plane Read Functionality
Data Storage Drive Rebuild with Parity Generation Offload Using Peer-to-Peer Data Transfers
Data Storage Device with Syndrome Weight Minimization for Data Alignment
Storage System and Method for Using Memory Allocated in a Host for Read Data as a Host Memory Buffer
Page Modification Encoding and Caching
Applying Endurance Groups To Zoned Namespaces
Calibrating Non-Volatile Memory Read Thresholds
Patent:
10,998,041 →
Application:
16/869,424 →
Capacitor Die for Stacked Integrated Circuits
Adaptive Folding for Integrated Memory Assembly
Semiconductor Device Including Vertical Bond Pads
Storage System and Method for Host Memory Access
Flip-Chip Package with Reduced Underfill Area
Method and Apparatus to Generate Zero Content Over Garbage Data When Encryption Parameters Are Changed
Storage System and Method for Command Execution Ordering by Security Key
Storage System and Method for Fast Low-Density Parity Check (LDPC) Encoding
Patent:
11,138,065 →
Application:
16/878,910 →
Systems and Methods for Power Management in a Data Storage Device
Patent:
11,137,823 →
Application:
16/879,595 →
Use Of Surplus Erase Block Pairs In Super Block Formation
Scrambling Using Different Scrambling Seeds for Defect Reduction and Improved Programming Efficiency
Shaped and Optimized Power Cycles
Patent:
11,126,254 →
Application:
16/883,897 →
Moving Change Log Tables to Align to Zones
Data Integrity Protection Of ZNS Needs
Data Integrity Protection Of SSDs Utilizing Streams
ZNS Parity Swapping to DRAM
Parity Swapping to Dram
Patent:
11,138,066 →
Application:
16/884,577 →
Rate Limit on the Transitions of Zones to Open
Patent:
11,126,378 →
Application:
16/885,073 →
Rate Limit On The Transitions Of Streams To Open
Erase Operation Reattempt To Recover Misidentified Bad Blocks Resulting From Consecutive Erase Failures
Patent:
11,152,071 →
Application:
16/885,147 →
System To Identify Aggressor Blocks Causing Back To Back Erase Failure
Detecting Problematic Voltage Signals from Charge Pumps
Patent:
11,073,570 →
Application:
16/885,655 →
Tiered Read Reference Calibration
Patent:
10,991,444 →
Application:
16/885,775 →
Programmable Processor in an Integrated Memory Assembly
Data Shaping for Integrated Memory Assembly
On-Chip-Copy for Integrated Memory Assembly
Integrated Electronic Element Module, Semiconductor Package, and Method for Fabricating the Same
Data Storage Device with Foggy-Fine Program Sequence for Reducing Neighbor Wordline Interference
Pre-Charge Ramp Rate Control For Peak Current Based On Data Latch Count
Storage System and Method for Smart Folding
Patent:
11,036,407 →
Application:
16/888,017 →
Pre-Charge Timing Control for Peak Current Based on Data Latch Count
Ramp Rate Control For Peak and Average Current Reduction of Open Blocks
Multi-Stage Voltage Control for Peak and Average Current Reduction of Open Blocks
Storage System, Host, and Method for Extended and Imaginary Logical-to-Physical Address Mapping
Storage System and Method for Media-Based Fast-Fail Configuration
Redundancy Data in Integrated Memory Assembly
Patent:
11,068,342 →
Application:
16/889,459 →
Read Threshold Calibration Using Multiple Decoders
Training Ensemble Models To Improve Performance In The Presence Of Unreliable Base Classifiers
Storage System and Method for Segregating Outliers in a Virtualization System
Storage System and Method for Host-Assisted Memory Block Color Coding for Faster Media Search
Effective Key Management For Data Encryption and Decryption
Die Memory Operation Scheduling Plan for Power Control in an Integrated Memory Assembly
Storage System and Method for Using Proactive Device Timeout Information
Adaptive Erase Voltage Based on Temperature
Storage System and Method for Storing Scalable Video
Patent:
11,140,445 →
Application:
16/891,802 →
Content-Aware Storage System and Method for Use Therewith
Ball Grid Array Substrate
Storage System and Method for Retention-Based Zone Determination
Dual Data Protection In Storage Devices
Patent:
11,170,869 →
Application:
16/893,204 →
Semiconductor Device Package Having Cover Portion with Curved Surface Profile
Attribute Mapping in Multiprotocol Devices
Controlled Die Asymmetry During MLC Operations For Optimal System Pipeline
Neural Network Data Updates Using in-Place Bit-Addressable Writes Within Storage Class Memory
Predicting Host Access Rates for Variable Bit Rate Data Streams Using a Data Storage Controller
Electrostatic Discharge Circuit Using Booster Cell
Zone Allocation for Data Storage Device Based on Zone Reset Behavior
Physical Defect Detection in an Integrated Memory Assembly
Patent:
11,114,178 →
Application:
16/897,724 →
Bumped Pad Structure
Memory Controller for Resolving String to String Shorts
Systems and Methods for Configuring a Data Storage Device
Storage System and Method for Frame Trimming to Optimize Network Bandwidth
Self-Data-Generating Storage System and Method for Use Therewith
QLC Programming Method with Staging of Fine Data
Secure Optical Communication Link
High-Throughput Out-of-Order Cipher Text Stealing
Read Latency Reduction through Command and Polling Overhead Avoidance
Storage System and Method for Enabling a Software-Defined Dynamic Storage Response
Removable Memory Card with Efficient Card Lock Mechanism and Pads Layout
Storage System and Method for Enabling Partial Defragmentation Prior to Reading in Burst Mode
Multi-Level Read After Heating Event in Non-Volatile Storage
Patent:
11,043,266 →
Application:
16/901,524 →
Detection of Compromised Storage Device Firmware
Quality of Service Based Arbitrations Optimized for Enterprise Solid State Drives
Multiple Sets of Trim Parameters
Program Verify Adaptation for Memory Devices
Storage System and Method for Object Monitoring
Background Interface Training Using Secondary Senses
Patent:
11,127,438 →
Application:
16/904,255 →
Multi-Function Sd Card
Mode Handling in Multi-Protocol Devices
Mapping for Multi-State Programming of Memory Devices
Data Storage System for Improving Data Throughput and Decode Capabilities
Hybrid Erase Mode for High Data Retention in Memory Device
Patent:
11,127,467 →
Application:
16/906,497 →
Command Sequence for Hybrid Erase Mode for High Data Retention in Memory Device
Patent:
11,120,880 →
Application:
16/906,516 →
Storage System and Method for Using Host-Assisted Variable Zone Speed Grade Modes to Minimize Overprovisioning
Nvm Endurance Group Controller Using Shared Resource Architecture
Memory Array Containing Capped Aluminum Access Lines and Method of Making the Same
Peer Storage Compute Sharing Using Memory Buffer
On-Chip Parity Buffer Management for Storage Block Combining in Non-Volatile Memory
Patent:
11,138,071 →
Application:
16/908,147 →
Accelerating Binary Neural Networks Within Latch Structure of Non-Volatile Memory Devices
Color Changing Storage Device Housing
Internal Thermal Transfer for Memory Device
Function Processing Using Storage Controllers for Load Sharing
Predictive Caching in Device for Media Seek in Playback or Scrolling
Very Low Complexity SECDED Codes
Symbol-Based Variable Node Updates for Binary Ldpc Codes
Encoding and Decoding of Hamming Distance-Based Binary Representations of Numbers
Dual-Interface Storage System and Method for Use Therewith
Methods and Apparatus for Enhancing Uber Rate for Storage Devices
Optimizations for Variable Sector Size in Storage Device Namespaces
Fast Copy Through Controller
Patent:
11,177,012 →
Application:
16/910,905 →
Storage Capacity Recovery Source Selection
Data Storage System and Method for Multiple Communication Protocols and Direct Memory Access
Low Complexity Conversion to Montgomery Domain
Low Complexity Conversion to Montgomery Domain
Adaptive Context Metadata Message for Optimized Two-Chip Performance
Extending Operating Temperature of Storage Device
Multi-Level Cell Programming Using Optimized Multiphase Mapping With Balanced Gray Code
Data-Assisted Ldpc Decoding
Patent:
11,159,176 →
Application:
16/913,044 →
Distributed Function Processing with Estimate-Based Scheduler
Apparatus and Method of Detecting Potential Security Violations of Direct Access Non-Volatile Memory Device
Just-In-Time Post-Processing Computation Capabilities for Encrypted Data
Storage System and Method for Balanced Quad-Level Cell (QLC) Coding with Margin for an Internal Data Load (IDL) Read
Storage System and Method for Direct Quad-Level Cell (QLC) Programming
Application-Based Storage Device Configuration Settings
Write Abort Error Detection in Multi-Pass Programming
SSD Operation in a Nonoptimal Memory Environment
Data Storage Selection Based on Data Importance
Content-Based Data Storage
Low Power State Staging
Completion Entry Throttling Using Host Memory
Operation-Deterministic Write Operations For Data Recovery And Integrity Checks
Efficient Estimator of Min-Entropy
Printed Circuit Board Compensation Structure for High Bandwidth and High Die-Count Memory Stacks
Distributed Grouped Terminations for Multiple Memory Integrated Circuit Systems
Power-Endurance Modes for Data Center Solid-State Drives
Storage Device Feature Extraction Optimization
Dual Sense Bin Balancing In NAND Flash
Variable Performance Storage Devices
Automatic Transcoding of Media Data in a Data Storage Device
Patent:
11,184,650 →
Application:
16/917,458 →
Proactive Storage Operation Management
Accessing Shared Partitions on a Storage Drive of a Remote Device
Managing Storage Device Compute Operations
Decoder for Irregular Error Correcting Codes
Patent:
11,190,219 →
Application:
16/917,870 →
Machine Learning For Temperature Compensation
Detecting Last Page Written in Multi-Plane Non-Volatile Memory
Modularized Multi-Purpose Storage System
Data Access in Data Storage Device Including Storage Class Memory
Read Level Tracking and Optimization
Thermal Region Tags and Thermal Region Outlier Detection
Method and Device for Covertly Communicating State Changes
Bounded Latency and Command Non Service Methods and Apparatus
Method and Apparatus for Cache Write Overlap Handling
Method and Apparatus for Cache Write Overlap Handling
Wireless Security Protocol
Methods and Systems for Password Protection of Defined Spaces Within a Memory Card
Method and System Involving Degradation of Non-Volatile Memory Based on Write Commands and Drive-Writes
Zoned Block Command to Stream Command Translator
Intelligent Wide Port Phy Usage
Content Aware Decoding Method And System
Content Aware Decoding Method and System
Quality Of Service Based Arbitrations Optimized For Enterprise Solid State Drives
Parallel Boot Execution Of Memory Devices
Logical And Physical Address Field Size Reduction By Alignment- Constrained Writing Technique
Package Process, Daf Replacement
Data Storage Systems and Methods for Improved Recovery After a Write Abort Event
Multi-State Programming for Memory Devices
Data Storage Server with on-Demand Media Subtitles
Incomplete Write Group Journal
Scheduling Access Commands for Data Storage Devices
Efficient Power Management Modes for Multiple Memory Devices
Spinel Containing Magnetic Tunnel Junction and Method of Making the Same
Patent:
11,176,981 →
Application:
16/944,758 →
Spinel Containing Magnetic Tunnel Junction and Method of Making the Same
Patent:
11,217,289 →
Application:
16/944,826 →
Instant and Permanent Self-Destruction Method in 3D Nand for Data Security Purpose
Patent:
11,133,074 →
Application:
16/984,478 →
Multiferroic-Assisted Voltage Controlled Magnetic Anisotropy Memory Device and Methods of Manufacturing the Same
Multiferroic-Assisted Voltage Controlled Magnetic Anisotropy Memory Device and Methods of Manufacturing the Same
Periodic Reduced Word Line Bias Which Increases Channel Boosting
Delaying Random Data Relocation For Reducing Write Amplification In Storage Devices
Enhanced Read-Ahead Capability for Storage Devices
Reducing Keep-Out-Zone Area for a Semiconductor Device
Cam Storage Schemes and Cam Read Operations for Detecting Matching Keys with Bit Errors
Invalidation Data Area for Cache
Data Storage Device and Method for Adaptive Command Completion Posting
Memory Device Containing Selector with Current Focusing Layer and Methods of Making the Same
Patent:
11,271,040 →
Application:
17/075,980 →
Low Resistance Multi-Layer Electrode for Phase Change Memory and Methods of Making the Same
Recovery of Validity Data for a Data Storage System
Geometry-Aware Command Scheduling
Interleaved Host Reset and Next Re-Initialization Operations
All Bit Line Sensing for Determining Word Line-to-Memory Hole Short Circuit
Patent:
11,309,035 →
Application:
17/098,831 →
Processor in Non-Volatile Storage Memory
Supervised Learning With Closed Loop Feedback To Improve Input Output Consistency Of Solid State Drives
Sloped Interconnector for Stacked Die Package
Side Contact Pads for High-Speed Memory Card
Assisted Multimedia Content Enhancement
Multi-State Programming for Memory Devices
Method and System for Identifying Erased Memory Areas
Semiconductor Device Including Vertical Wire Bonds
Direct Host Access to Storage Device Memory Space
Enhanced Memory Device Architecture for Machine Learning
Dynamic Calibration of Frequency and Power Storage Interface
Managing Data for a Data Storage System
System Data Storage Mechanism Providing Coherency and Segmented Data Loading
Decryption and Variant Processing
Adaptive Program Verify Scheme For Performance Improvement
Straight Wirebonding of Silicon Dies
Nonvolatile Memory with Encoding for Foggy-Fine Programming with Soft Bits
Read Threshold Calibration for Nonvolatile Memory with Encoded Foggy-Fine Programming
Soft Bit Reference Level Calibration
Read Integration Time Calibration for Non-Volatile Storage
Adjacent Memory Cell Interference Mitigation
Fast Verification of Non-Volatile Data Integrity
Soft Information for Punctured Bit Estimation in a Data Storage Device
Matrix-Vector Multiplication Using Sot-Based Non-Volatile Memory Cells
Sot-Based Spin Torque Oscillators for Oscillatory Neural Networks
Apparatus and Methods for Magnetic Memory Devices with Magnetic Assist Layer
Nonvolatile Memory with on-Chip Encoding for Foggy-Fine Programming
Power Reduction During Open and Erased Block Reads of Memory Based on the Position of Last Written Word Line of a Memory Block
Adaptive Mixed Digital and Analog Computational Storage Systems
Semiconductor Device Including Coupled Bond Pads Having Differing Numbers of Pad Legs
Semiconductor Device with Reduced Stress Die Pick and Place
Semiconductor Device Including Semiconductor Dies of Differing Sizes and Capacities
Overhead Reduction in Data Transfer Protocol for NAND Memory
Boosted Boot Procedure By Background Re-Arrangement Of Read Patterns
Command Management Using Allocated Command Identifier Pools
Low Light Surveillance System with Dual Video Streams
Host Load Based Dynamic Storage System for Configuration for Increased Performance
Patent:
11,379,137 →
Application:
17/176,633 →
Audio Privacy Protection for Surveillance Systems
Overhead Reduction in Data Transfer Protocol for Data Storage Devices
Storage System and Method for Time-Based Data Retrieval
Storage System and Method for Storage Management in Multi-Channel, Variable-Bit-Rate Systems
Using Scheduling Tags in Host Compute Commands to Manage Host Compute Task Execution by a Storage Device in a Storage System
Storage System and Method for Time-Duration-Based Efficient Block Management and Memory Access
Method and System for Improving Word Line Data Retention for Memory Blocks
Patent:
11,386,969 →
Application:
17/176,867 →
Operating Parameters for Non-Volatile Memory Devices
Local Data Compaction for Integrated Memory Assembly
Integrated Non-Volatile Memory Assembly with Address Translation
Non-Volatile Memory with Intelligent Compute Task Distribution
Storage System and Method for Token Provisioning for Faster Data Access
Storage System and Method for Device-Determined, Application-Specific Dynamic Command Clustering
Storage System and Method for Data-Driven Intelligent Thermal Throttling
Intelligent Memory Wear Leveling
Command Slot Management for Memory Devices
Fixed Size Soft Bit Lossy Compression in Flash Memory
Storage System and Method for Providing a Dual-Priority Credit System
Storage System and Method for Event-Driven Data Stitching in Surveillance Systems
Storage System and Method for Dynamic Selection of a Host Interface
Wear Leveling Methods For Zoned Namespace Solid State Drive
Coherent Access to Persistent Memory Region Range
Asynchronous Neural Network Systems
Application:
17/178,809 →
Publication:
US 2022/0044113
Power Shaping And Peak Power Reduction By Data Transfer Throttling
Surveillance Video Streams with Embedded Object Data
Data Storage Device and Method for Enabling a Compare Command with Built-In Data Transformations
Patent:
11,372,559 →
Application:
17/179,930 →
Memory Card Operable with Multiple Host Interfaces
Data Storage Device and Method for Real-Time Data Locking in Surveillance Storage
Storage System and Method for Dual Fast Release and Slow Release Responses
Data Storage Device and Method for Enabling Endurance Re-Evaluation
Connector for Printed Circuit Board (Pcb) Memory Drive
Zoned Namespace Limitation Mitigation Using Sub Block Mode
Read Handling in Zoned Namespace Devices
Command Prioritization to Reduce Latencies of Zone Commands
Hold-Up Capacitance Health Measurement With Current Leakage Detection
Management of Operations During Exception Handling in Memory
Application:
17/180,656 →
Publication:
US 2022/0121391
Delayed Thermal Throttling and Associated Data Routing Techniques
Data Integrity Check for Writing Data in Memory
Resource Utilization Tracking Within Storage Devices
Automatic Flexible Schema Detection and Migration
Data Storage Device and Method for Enabling Higher Lane Utilization in Run Time Via Device Hints on Workload Patterns
System and Method for Die Crack Detection in a CMOS Bonded Array
System and Method for Warpage Detection in a CMOS Bonded Array
Storage System and Method for a Hybrid Quad-Level Cell (QLC) Write Scheme for Reduced Random Access Memory (RAM) Footprint
Query Compiler for Record Filtering
Data Storage Device Database Management Architecture
High Throughput, Low Power, High Parity Architecture for Database Ssd
Emulation of Code-Description Tables on Sql Databases Using Enum Data Type
Qlc Data Programming
NVMe Simple Copy Command Support Using Dummy Virtual Function
Relocation Flow Using CbA Technology
Devices and Methods for Optimized Fetching of Multilingual Content in Media Streaming
Elastic Buffer Based Asymmetric Pipeline FIFO Process
Systems and Methods for Power and Performance Improvement Through Dynamic Parallel Data Transfer Between Device and Host
Transformation of Data to Non-Binary Data For Storage in Non-Volatile Memories
Apparatus and Method for Regulating Available Storage of a Data Storage System
Storage System and Method for Performing Random Read
Storage System and Dual-Write Programming Method with Reverse Order for Secondary Block
Storage System and Method for Detecting and Utilizing Wasted Space Using a File System
Predictive Performance Indicator for Storage Devices
Storage System with Encrypted Data Storage Device Telemetry Data
Deduplication of Storage Device Encoded Data
Allocating Data Storage Based on Aggregate Duplicate Performance
Data Storage Device Performance Prediction Based on Valid Fragment Count
Data Storage Devices and Related Methods to Secure Host Memory Buffers with Low Latency
Storage Delta Compression
LDPC Encoding For Memory Cells With Arbitrary Number Of Levels
Efficient TLP Fragmentations In Extended LBA Environment
Storage System and Method for Dynamic Allocation of Secondary Backup Blocks
Storage System and Method for Using Read and Write Buffers in a Memory
Usage of Data Mask in Dram Write
Patent:
11,385,963 →
Application:
17/183,784 →
Variable QoS Management of Multiple Data Streams
Mixed Mode Block Cycling for Intermediate Data
Data Aggregation In ZNS Drive
Host-Managed Hardware Compression With Zoned Namespaces
Systems and Methods for Use with Recurrent Neural Networks
Relinking Scheme in Sub-Block Mode
Data Storage Device Enabling Latches of Non-Volatile Memory Dies for Use as Externally-Accessible Volatile Memory
Using Over Provisioning Space for Selectively Storing Block Parity
Method and Apparatus for Debugging Integrated Circuit Systems Using Scan Chain
Command Draining Using Host Memory Buffer
Data Storage With Improved Data Transfer
Effective PCIe Utilization by PCIe TLP Coalescing
Efficient Data Storage Usage Associated with Ungraceful Shutdown
Detection Of Page Discrepancy During Read Threshold Calibration
Device Interrupt Coalescing With Various Host Behaviors
Dual Voltage High Speed Receiver with Toggle Mode
Decreasing Physical Secure Erase Times in Solid State Drives
Detection Of Scattered Data Locations
Early Transition To Low Power Mode For Data Storage Devices
NVMe Persistent Memory Region Quick Copy
Dual Data Ports with Shared Detection Line
Semiconductor Device Package Having Thermally Conductive Pathways
Wire Bonding For Semiconductor Devices
Identified Zones For Optimal Parity Sharing Zones
Identification and Classification of Write Stream Priority
Pre-Fetch of Data Using Seek Intervals
Managing Overwrite Data Within Solid State Drives
Active Low-Power Termination
Error Correction Based on Physical Characteristics for Memory
Electrical Overlay Measurement Methods and Structures for Wafer-to-Wafer Bonding
Data Storage With Improved Read Parallelism
Packaged Memory Device with Flip Chip and Wire Bond Dies
Data Storage That Controls Decode Performance By Changing Program PLC
Spinel Containing Magnetic Tunnel Junction and Method of Making the Same
Electrical Overlay Measurement Methods and Structures for Wafer-to-Wafer Bonding
Revised Host Command Generation For Unaligned Access
Dynamic Valley Searching in Solid State Drives
Erase Technique for Checking Integrity of Non-Data Word Lines in Memory Device and Corresponding Firmware
Patent:
11,335,419 →
Application:
17/197,762 →
Data Storage Device and Method for Application Identifier Handler Heads-Up for Faster Storage Response
Simplified High Capacity Die and Block Management
Power Reallocation for Memory Device
TLC Data Programming With Hybrid Parity
Storage System and Method for Using Subcodes and Convolutional-Based LDPC Interleaved Coding Schemes with Read Threshold Calibration Support
System and Method for Detection of Defects in Semiconductor Devices
Magnetoresistive Memory Device Including a Reference Layer Side Dielectric Spacer Layer
Management of Thermal Throttling in Data Storage Devices
Thermally Conductive Non-Oil Bleed Liquid Thermal Interface Materials
Application:
17/204,552 →
Publication:
US 2022/0298305
Idle-Power Mitigation Circuit
Communication with a Data Storage Device Using an Emulated Wi-Fi Captive Portal
Secure Data Storage Device and Method of Encryption
Management Of A Debug Buffer Based On Priority Information
Fast Initialization Of Secure HMB
Extensible Storage System And Method
Optimized Threshold Translation From Serialized Pipeline
Magnetoresistive Memory Device Including a Magnesium Containing Dust Layer
Magnetoresistive Memory Device Including a Magnesium Containing Dust Layer
Key Based Partial Data Restriction in Storage Systems
Prediction-Based Selective Flushing Of Data To Memory
System and Method for Mitigating Effect of Erase Cells on Adjacent Cells
Dynamic Read Threshold Calibration
Content Aware Decoding Using Shared Data Statistics
Memory Device With Reinforcement Learning With Q-Learning Acceleration
Wear Leveling in Non-Volatile Memory
Level Dependent Error Correction Code Protection in Multi-Level Non-Volatile Memory
Technique for Adjusting Read Timing Parameters for Read Error Handling
Patent:
11,367,491 →
Application:
17/213,997 →
Printed Circuit Board Trace for Galvanic Effect Reduction
Patent:
11,234,327 →
Application:
17/214,215 →
Storage System and Method for Automatic Defragmentation of Memory
Data Address Management In Non-Volatile Memory
Switch Based Bga Extension
Interrupt Coalescing Protection Logic
Security Device for a Data Storage Device
Data Storage Device Encryption
Data Storage Device Encryption
Expandable Memory for Use with Solid State Systems and Devices
Pre-Erasure of Memory in Storage Devices
Host Memory Buffer Allocation Management
Patent:
11,403,011 →
Application:
17/222,565 →
Priority-Based Data Movement
Enhanced D3-Cold And Faster Recovery
Storage System with Dual Submission Queue Doorbell Registers and Method for Use in a Multi-Tenant System
Method and System For Managing Memory Device
Solid State Drive Cache Eviction Policy By An Unsupervised Reinforcement Learning Scheme
Power Safe Offline Download
Data Storage Device and Method of Access
Semiconductor Device Package Having Thermally Conductive Layers for Heat Dissipation
Universal Serial Bus Voltage Reducing Adapter
Read Threshold Management and Calibration
Very Low Sized Zone Support for Storage Devices
State-By-State Program Loop Delta Detection Mode for Detecting a Defective Memory Array
Command Queue Order Adjustment in a Data Storage Device
Privacy Enforcing Memory System
Control Block Management in Storage Devices
Data Storage Device and Method for Preventing Accidental Updates and Deletions Using Data Versioning
Block Allocation for Multi-Ce/Die Structure Ssd
System and Method of Direct Write and Mapping of Data in a Non-Volatile Memory Having Multiple Sub-Drives
User Controlled Data-in for Lower and Middle Page in Mlc-Fine Qlc Memories
Fast Write on Merkle Tree for Secure Hmb
Printed Circuit Board with Stacked Passive Components
Cache Based Flow for a Simple Copy Command
Adaptive Soft-Bit Compression in Flash Memory
Patent:
11,456,758 →
Application:
17/239,057 →
Detection of Data Discrepancy After XOR Recovery
Bandwidth Allocation for Storage System Commands in Peer-to-Peer Environment
Adjustable Read Retry Order Based on Decoding Success Trend
Data Storage System and Method for Multiple Communication Protocols and Memory Access
Non-Volatile Memory with Optimized Read
Mechanism to Improve Driver Capability with Fine Tuned Calibration Resistor
Toggle Mode (TM) Coding With Circuit Bounded Array Memory
Thermoelectric Semiconductor Device and Method of Making Same
Patent:
11,444,001 →
Application:
17/314,712 →
Rolling Xor Protection in Efficient Pipeline
Methods and Systems for Object Level De-Duplication for Data Storage System
Storage System and Method for Data Recovery After Detection of an Uncorrectable Error
Processing Host Write Transactions Using a Non-Volatile Memory Express Controller Memory Manager
Multi-Fetching Data for Multi-Pass Programming within Storage Devices
Modified Distribution of Memory Device States
Patent:
11,462,279 →
Application:
17/319,756 →
Apparatus and Methods for Writing Random Access Memories
Storage System and Method for Dynamic Allocation of Control Blocks for Improving Host Write and Read
Storing Log And User Data In SSD With Independent Plane Operations
Substrate Component Layout and Bonding Method for Increased Package Capacity
High Voltage Protection for High-Speed Data Interface
Processing of Surveillance Video Streams Using Image Classification and Object Detection
Customized Thermal Throttling Using Environmental Conditions
Vertical Semiconductor Device with Side Grooves
Dynamic Command Scheduling for Storage System
Multi-Rate ECC Parity For Fast SLC Read
Utilizing Host Memory Buffers for Storage Device Recoveries
Patent:
11,487,439 →
Application:
17/331,958 →
Adaptive Read Scrub
Storage of Tree Data Structures
Storage of Tree Data Structures
Data Storage Device and Method for Object Detection and Tagging Quality of Service Based on Storage Workload
Data Storage Device and Method for Reliable Watermarking
Method To Use Flat Relink Table In HMB
Self-Adaptive Program Pulse Width for Programming 3D Nand Memory
Data Storage Device and Method for Legitimized Data Transfer
Data Storage Device and Method for Application-Defined Data Retrieval in Surveillance Systems
Dissimilar Write Prioritization in ZNS Devices
Dissimilar Write Prioritization in ZNS Devices
Circuit to Reduce Gating Overall System Performance
Patent:
11,380,417 →
Application:
17/338,595 →
Combined Semiconductor Device Packaging System
Data Management For Efficient Low Power Mode Handling In A Storage Device
Data Storage Device and Method for Efficient Image Searching
Voltage-Controlled Magnetic Anisotropy Memory Device Including an Anisotropy-Enhancing Dust Layer and Methods for Forming the Same
Voltage-Controlled Magnetic Anisotropy Memory Device Including an Anisotropy-Enhancing Dust Layer and Methods for Forming the Same
Voltage-Controlled Magnetic Anisotropy Memory Device Including an Anisotropy-Enhancing Dust Layer and Methods for Forming the Same
Detecting Latent Defects in a Memory Device During an Erase Operation Based on Physical and Logical Segment Fail Bits
Soft Bit Reference Level Calibration Using Decoded Data
Asynchronous Fifo for Power-Domain Crossing
Substrate Bonding Pad Having a Multi-Surface Trace Interface
Managing Persistent Memory Regions Across Multiple Protocols
Data Storage Device and Method for Memory Operation and Iterative Polling
Monolithic Surface Mount Passive Component
Encoding Digital Videos Using Controllers of Data Storage Devices
Data Storage Device Having Predictive Analytics
System and Method of Data Writes and Mapping of Data for Multiple Sub-Drives
Ethernet in Data Storage Device
Systems and Methods of Determining Degradation in Analog Compute-in-Memory (Acim) Modules
Systems and Methods of Compensating Degradation in Analog Compute-In-Memory (ACIM) Modules
Data Storage Device and Method for Auto-Peeling of Surveillance Video Content to Increase Archival Storage
Multiple Function Level Reset Management
A Method of Forming a Semiconductor Device Including Vertical Contact Fingers
Storage Devices Hiding Parity Swapping Behavior
Snapback Electrostatic Discharge Protection For Electronic Circuits
Enhanced Digital Signal Processor (Dsp) Nand Flash
Video Processing in a Data Storage Device
Latency On Indirect Admin Commands
Fast Garbage Collection In Zoned Namespaces SSDs
Dual Time Domain Control for Dynamic Staggering
Patent:
11,508,450 →
Application:
17/351,455 →
Data Storage Device and Method for Progressive Fading for Video Surveillance Systems
Storage System and Method for Decision-Based Memory Read Threshold Calibration
Patent:
11,488,684 →
Application:
17/352,953 →
Secure-Erase Prediction for Data Storage Devices
Performing Background Operations During Host Read in Solid State Memory Device
Solder Paste Stencil with Aperture Wall Coating
Systems and Methods for Power Management in a Data Storage Device
Semiconductor Device Package Having a Ball Grid Array with Multiple Solder Ball Materials
Application:
17/354,096 →
Publication:
US 2022/0406695
Semiconductor Device Including Conductive Bumps to Improve Emi/Rfi Shielding
Frozen Time Cache for Multi-Host Read Operations
Aligned Command Based Firmware Architecture for Unaligned Write Handling
Secured Firmware with Anti-Malware
Non-Volatile Storage with Progressive Writes
Patent:
11,482,292 →
Application:
17/356,331 →
Data Storage Systems and Methods for Improved Data Relocation Based on Read-Level Voltages Associated with Error Recovery
Multi-Phased Programming with Balanced Gray Coding
Multi-State Programming for Memory Devices
Write Performance by Relocation During Sequential Reads
Efficient Handling of Background Operations for Improving Sustained Performance of Host Reads and Writes
Enhanced Word Line Stripe Erase Abort Detection
Providing Priority Indicators for NVMe Data Communication Streams
Memories with End-to-End Data Protection Using Physical Location Check
Patent:
11,429,485 →
Application:
17/357,759 →
Address Translation for Storage Device
Error Recovery Handling
Dynamic Multi-Stage Decoding
Systems and Methods for Priority Command Data Fetching Management
Data Retention-Specific Refresh Read
Site-Based Calibration of Object Detection Parameters
Bias for Data Retention in Fuse ROM and Flash Memory
Tiered Storage System with Defragmentation Based on Weighted Flash Fragmentation Factor
Pulsed Bias for Power-Up or Read Recovery
Magnetoresistive Memory Device Including a Plurality of Reference Layers
Multi-Level Cell Programming Using Optimized Multiphase Mapping with Balanced Gray Code
Read Level Tracking and Optimization
Remote Registration of a Data Storage Device with Biometric Authentication
Systems and Methods for Fragmentation Management in Host Buffers
Distributed Exception Handling in Solid State Drives
Parity-Based Redundant Video Storage Among Networked Video Cameras
High Bit Rate Communication Interface with Common Mode Voltage Adjustment
Peer-to-Peer Media Streaming from an Edge Data Storage Device to a Browser
Semiconductor Wafer Transfer Arm
Passcode Authentication Based Data Storage Device
Lock or Unlock Indicator on a Data Storage Device
Method and Apparatus to Control Bi-color LEDs on Enterprise and Datacenter Solid State Drive (E3) Form Factor
Semiconductor Device Package Die Stacking System and Method
Hardware Accelerated Discretized Neural Network
Non-Cure and Cure Hybrid Film-On-Die for Embedded Controller Die
Isolating Problematic Memory Planes to Avoid Neighbor Plan Disturb
Optimized Neural Network Data Organization
Foggy-Fine Programming for Memory Cells with Reduced Number of Program Pulses
Data Storage Device with Data Verification Circuitry
UFS Out of Order Hint Generation
Method and Storage System with a Non-Volatile Bad Block Read Cache Using Partial Blocks
Obtaining Threshold Voltage Measurements for Memory Cells Based on a User Read Mode
Non-Volatile Memory Die with Deep Learning Neural Network
Adversarial Information Bottleneck Strategy for Improved Machine Learning
System and Method for Memory Hang Recovery Using a Distributed Power Management System
Global Extension of a Logical-to-Physical Region of a Data Storage Device
Solution For Super Device Imbalance In ZNS SSD
Purposeful Super Device Imbalance For ZNS SSD Efficiency
Super Block Allocation Across Super Device In ZNS SSD
Application:
17/412,151 →
Publication:
US 2023/0075329
Controlled Imbalance In Super Block Allocation In ZNS SSD
Asymmetric Read Sense
Cumulative Wordline Dispersion and Deviation for Read Sense Determination
Cell Statistics Generator for Nvm Devices
Testing Apparatus for Temperature Testing of Electronic Devices
NVMe Dual Port Enterprise SSD Optimization
Efficient Data Path In Compare Command Execution
On-Chip Non-Volatile Memory (Nvm) Search
Data Transfer Management From Host Buffers
Read Level Tracking By Random Threshold Movement With Short Feedback Loop
Optimizing Recovery Of Recurrent Blocks Using Bloom Filter
Host Memory Buffer Cache Management
Mlm Mapped Nand Latch
Dual SLC/QLC Programming and Resource Releasing
Zoned Block Command To Stream Command Translator
Storage Devices Hiding Parity Swapping Behavior
Keeping Zones Open With Intermediate Padding
Selective Device Power State Recovery Method
Immediate Partial Host Buffer Fetching
Embedded Physical Layers with Passive Interfacing for Configurable Integrated Circuits
Testing Apparatus for Data Storage Devices
Parallel Commands Overlap Detection Based On Queue-Depth
Low Resistance Monosilicide Electrode for Phase Change Memory and Methods of Making the Same
Housings for Electronic Devices and Memory Devices
3-Dimensional NAND Flash Layer Variation Aware SSD Raid
Methods and Systems for Implementing Redundancy in Memory Controllers
Endurance Groups ECC Allocation
Patent:
11,556,274 →
Application:
17/464,384 →
Storage System and Method for Storing Logical-to-Physical Address Table Entries in a Codeword in Volatile Memory
Patent:
11,550,658 →
Application:
17/465,165 →
Storage System and Method for Performing a Targeted Read Scrub Operation During Intensive Host Reads
Rate Limit On The Transitions Of Zones To Open
Shaped And Optimized Power Cycles
Method and System for Maintenance Allocation Between NVM Groups
Selective HMB Backup In NVM For Low Power Mode
Patent:
11,531,473 →
Application:
17/471,608 →
Cross-Point Spin-Transfer Torque Magnetoresistive Memory Array and Method of Making the Same
Sideband Information Over Host Interface Considering Link States
Recovery From HMB Loss
Non-Volatile Memory with Reverse State Program
Storage System and Method for Prediction-Based Pre-Erase of Blocks to Improve Sequential Performance
Regular Expression Filter for Unicode Transformation Format Strings
Semiconductor Device Package Having Multi-Layer Molding Compound and Method
Fabric Interconnection for Memory Banks Based on Network-on-Chip Methodology
Data Storage Device and Method for File-Based Interrupt Coalescing
Semiconductor Device Package Mold Flow Control System and Method
NAND Dropped Command Detection and Recovery
Interleaved Ecc Coding for Key-Value Data Storage Devices
Continuous NAND Data-Transfer Using Filling Rate Evaluation Approach
Support Higher Number of Active Zones in ZNS SSD
System and Method for Adaptive Command Fetch Aggregation
Distribution of Logical-to-Physical Address Entries Across Multiple Memory Areas
On-Chip-Copy for Integrated Memory Assembly
Storage System and Method for Program Reordering to Mitigate Program Disturbs
Hybrid Memory Management of Non-Volatile Memory (Nvm) Devices for Use with Recurrent Neural Networks
Hybrid Memory Management of Non-Volatile Memory (Nvm) Devices for Use with Recurrent Neural Networks
Systems and Methods for Key-based Indexing in Storage Devices
Processor Instructions for Iterative Decoding Operations
Patent:
11,522,563 →
Application:
17/500,653 →
Systems and Methods for Allocating Blocks of Memory to Multiple Zones Associated with Corresponding Error Correction Mechanisms
Method and System for Decoding Data based on Association of First Memory Location and Second Memory Location
Non-Volatile Memory with Pre-Trained Model and Inference Circuit
Program Verify Adaptation for Non-Volatile Memory
Data Storage Devices, Systems, and Related Methods for Grouping Commands of Doorbell Transactions from Host Devices
UECC Failure Handling Method
Semiconductor Device Package Having Improved Conductive Stub Coverage
Direct Write Operation for Quad-level Cell Based Data Storage Devices
Wire Bond Pad Design for Compact Stacked-Die Package
Stacked Ssd Semiconductor Device
Application:
17/517,911 →
Publication:
US 2023/0137512
Reduce Command Latency Using Block Pre-Erase
Semiconductor Device With Unbalanced Die Stackup
Dynamic Controller Buffer Management and Configuration
Resource Usage Arbitration in Non-Volatile Memory (Nvm) Data Storage Devices with Artificial Intelligence Accelerators
Storage System and Method for Multi-Cell Mapping
Method to Ensure Message Arrival Before a Message Pointer
Self-Guided Placement of Memory Device Component Packages
Data Auto-Relocation in an Integrated Memory Assembly
Method and Storage System with a Layered Caching Policy
Data Storage System for Improving Data Throughput and Decode Capabilities
Dynamic Multi-Stage Decoding
Block Budget Enhancement Mechanisms for Memory
Ecc Parity Biasing for Key-Value Data Storage Devices
Pre-Validation Of Blocks For Garbage Collection
Generating Transcoded Media Using Data Storage Devices
Secure Stream Buffer on Network Attached Storage
Block Erase Type Detection Using Bit Count Check
Semiconductor Device Including a Suspended Reinforcing Layer and Method of Manufacturing Same
Trusted Systems for Decentralized Data Storage
Ball Grid Array Substrate
Full Die Recovery In ZNS SSD
Centralized SRAM Error Location Detection and Recovery Mechanism
Thermal Surrogate for a Data Storage Device
Mold Compound Dispensing System and Method
Logical to Encoded Value Table in Data Storage Device
Host Memory Buffer (HMB) Random Cache Access
Patent:
11,604,735 →
Application:
17/541,028 →
Data Storage Device and Method for Providing a Temperature-Driven Variable Storage Capacity Point
Data Storage Device and Method for Accidental Delete Protection
Command Queuing for Data Storage Devices
Management of Composite Cold Temperature for Data Storage Devices
Enterprise Host Memory Buffer
Memory Matched Low Density Parity Check Coding Schemes
Non-Volatile Memory with on-Chip Principal Component Analysis for Generating Low Dimensional Outputs for Machine Learning
Ssd Wafer Device and Method of Manufacturing Same
Maximum Data Transfer Size Per Tenant And Command Type
Storage System and Method for Data Protection During Power Loss
Consensus Data Filtering in Proof of Space Blockchain Systems
Data Storage Method and System with Persistent Memory and Non-Volatile Memory
Parity Data for Non-Volatile Storage
Secure Wireless Communication System and Method
Secure Data Content Access System and Method
Image Group Classifier in a User Device
Ranking Images in an Image Group
Storage System and Method for Quantifying Storage Fragmentation and Predicting Performance Drop
Storage System and Method for Optimizing Write-Amplification Factor, Endurance, and Latency During a Defragmentation Operation
Optimizing Flash Memory Utilization for NVMe KV Pair Storage
Storage System and Method for Non-Blocking Coherent Re-Writes
Smart Relocation Scan Optimization
Translation Lookup and Garbage Collection Optimizations on Storage System with Paged Translation Table
Variable Length ECC Code According to Value Length in NVMe Key Value Pair Devices
System and Method for Big Number Hardware Multiplication for Cryptography
Maximizing Performance Through Traffic Balancing
Data Storage Device and Method for Data Protection Using Xor Parity
Reducing File Sizes for Media Content
Storage System and Method for Avoiding Clustering of Reads During a Program Suspend
Power Management for Storage Controllers
Readiness States for Partitioned Internal Resources of a Memory Controller
Application:
17/567,098 →
Publication:
US 2023/0214270
Low Latency Parity for a Memory Device
Content Aware Decoding In KV Devices
PCIe TLP Size And Alignment Management
Data Storage Device and Method for Memory-Die-State-Aware Host Command Submission
Semiconductor Device Including Differential Height Pcb
Data Storage Device and Method for Providing an Adaptive Data Path
Log File System (LFS) Invalidation Command and Operational Mode
Spin-Transfer Torque Magnetoresistive Memory Device with a Free Layer Stack Including Multiple Spacers and Methods of Making the Same
Cold Storage Partition Management in Proof of Space Blockchain Systems
Ovonic Threshold Switch Selectors with Electrodes Including Carbon and Metal
Data Storage Device Having Over-Voltage Detection and Protection
Microchannel Heat Sink for Datacenter Solid State Drives
Non-Volatile Memory with Enhanced Program Operation for Last State on Slow Plane
Data Storage Systems and Methods for Improved Recovery After a Write Abort Event
Storage System and Method for Implementing an Encoder, Decoder, and/or Buffer Using a Field Programmable Gate Array
Storage Device Optimizations in Proof of Space Blockchain Systems
Storage Device Throttling in Proof of Space Blockchain Systems
Storage Biasing for Solid State Drive Accelerators
Implied Streams
Non-Volatile Memory with Redundant Control Line Driver
Method of Making Magnetoresistive Memory Cell Over a Selector Pillar
Localized Onboard Socket Heating Elements for Burn-in Test Boards
Patent:
11,650,246 →
Application:
17/591,129 →
Method of Making Ovonic Threshold Switch Selectors Using Microwave Annealing
Voltage Sharing Across Memory Dies in Response to a Charge Pump Failure
Storage System and Method for Delaying Flushing of a Write Buffer Based on a Host-Provided Threshold
Keeping a Zone Random Write Area in Non-Persistent Memory
Memory Device Based Accelerated Deep-Learning System
Application:
17/592,953 →
Publication:
US 2023/0251792
Adjustment Of Storage Device Parameters Based On Workload Characteristics
Zoned Namespaces in Solid-State Drives
QLC Programming Method With Staging Of Fine Data
SSD Auxiliary Battery Power For Handling Ungraceful Shutdown With Host
Mitigating DBI Bit Flip Induced Errors
Semiconductor Device With Unbalanced Die Stackup
Dynamic Port Allocation In PCIe Bifurcation System
Method Of Handling Irregular MetaBlock Wear Leveling And UGSD Boot Time Improvement
DRAM-Less SSD With Secure HMB For Low Latency
Execution Condition Embedded In A Command Or A Request To Storage Device
Data Relocation With Protection For Open Relocation Destination Blocks
Systems, Devices, and Methods for Testing Integrated Circuits in Their Native Environments
Automatic Prediction Timers Adaptation
Instant Submission Queue Release
Combining Operations During Reset
Optimized Autonomous Defragmentation Of Storage Devices
DRAM-less SSD With HMB Cache Management
Complete And Fast Protection Against CID Conflict
Enclosure fitting for electronic device
Method of Thinning a Semiconductor Die
Die Location Based Logical Block Formation and Handling
Non-Volatile Cross-Bar Memory with on-Chip Processing Circuitry
Secure Metadata Protection
Semiconductor Device Package with Exposed Bond Wires
Resource Management For Solid State Drive Accelerators
Semiconductor Device with Protective Layer
Application:
17/673,150 →
Publication:
US 2023/0260949
Out of Order Data Transfer Hint Calibration
Semiconductor Devices Having Supportive Plating Structures
Dynamic Xor Bin Mapping in Memory Devices
Data Storage Device and Method for Responding to a Host-Specified Parameter of an Upcoming Burst Mode
Storage System and Method for Improving Read Latency During Mixed Read/Write Operations
Tombstone Prevention for a Surface Mount Device
Semiconductor Wafer and Semiconductor Dies Formed Therefrom Including Grooves Along Long Edges of the Semiconductor Dies
Write Updates Sorting During BKOPS Idle
Non-Volatile Memory with Intentional Overprogramming to Improve Short Term Data Retention Issue
Multiple Authorization Requests from a Data Storage Device
Cryptographic Keys for Authorization Requests from a Data Storage Device
Certificates in Data Storage Devices
Authorization Requests from a Data Storage Device to Multiple Manager Devices
Method and System For Managing Memory Device
Data Storage Device and Method for Host-Initiated Transactional Handling for Large Data Set Atomicity Across Multiple Memory Commands
Network Interface Card Implementing Composite Zoned Namespace Architecture
Cloud Storage Device Implementing Composite Zoned Namespace Architecture
Logical to Physical Mapping Management Using Low-Latency Non-Volatile Memory
Non-Volatile Storage System with Hybrid Slc Wear Leveling
Semiconductor Device With Optimized Underfill Flow
Application:
17/699,979 →
Publication:
US 2023/0299034
Extensible Storage System and Method
Adaptive-Feedback-Based Read-Look-Ahead Management System and Method
Data Storage Device With Enhanced Power Mode Management
Data Compression with Entropy Encoding
Dual Performance Trim for Optimization of Non-Volatile Memory Performance, Endurance, and Reliability
Method and System for Identifying Erased Memory Areas
Tray and Packaging Assembly for Data Storage Devices
Data Storage Device and Method for Executing a Low-Priority Speculative Read Command from a Host
Non-Volatile Memory Integrated with Artificial Intelligence System for Preemptive Block Management
Management of Thermal Shutdown in Data Storage Devices
Data Storage Device With Die-Based Enhanced Thermal Management
Storage Optimization Of CAT Table During Background Operations
Aligned And Unaligned Data Deallocation
Storage System and Folding Method for Enhanced Performance
Read Threshold Calibration for Cross-Temperature Long, Sequential Reads
Protocol Indicator for Data Transfer
Mesh Network-on-a-Chip (Noc) with Heterogeneous Routers
Micro Solder Joint and Stencil Aperture Design
DRAM-less SSD With Command Draining
Controlled System Management Based On Storage Device Thermal Load
Hiding Proof-of-Space in Blockchain Systems
Printed Circuit Board for Galvanic Effect Reduction
Hardware Accelerator Circuits for Near Storage Compute Systems
Speculative Command Processing Interface in Storage Systems
Storage System and Method for Host Memory Access
Clamped Semiconductor Wafers and Semiconductor Devices
Printed Circuit Board Having a Sacrificial Pad to Mitigate Galvanic Corrosion
Fused Command Handling
Tracking Data Usage in Storage Devices
Non-Volatile Memory with Atonomous Cycling
Relative Size Reduction of a Logical-To-Physical Table
Adaptive Multi-Stream Classification for Data Storage Systems
Semiconductor Device Package with Combined Contacts
Protective Enclosure for an Electronic Device
Storage System and Method for Preserving Overwritten Data to Allow a Future Rollback
DRAM-less SSD With Recovery From HMB Loss
Read Look Ahead Optimization According To NVMe Dataset Management Hints
Configurable Arithmetic HW Accelerator
Reducing Link Up Time In PCIe Systems
Non-Volatile Memory with Concurrent Sub-Block Programming
Printed Circuit Board with Embedded Bump Pads
Application:
17/726,990 →
Publication:
US 2023/0345633
Detection of Compromised Storage Device Firmware
Securing a Data Storage Device Against Rogue Hosts
Automated Overlay Regrouping
Video Group Classification Using Object Tracker
Group Classifier Training Using Video Object Tracker
Data Storage With Real Time Dynamic Clock Frequency Control
Back-to-Back Power Loss Protection
Enterprise Host Memory Buffer For DRAM-less SSD
Low Latency Block Cipher in Memory Devices
Flash-Translation-Layer-Aided Power Allocation in a Data Storage Device
Cross-Point Array with Threshold Switching Selector Memory Element
Data Storage Device and Method for Token Generation and Parameter Anonymization
Semiconductor Device Package with Coupled Substrates
Storage Compute Services for Encrypted Data
Allocation of Host Memory Buffer for Sustained Sequential Writes
Persistent Switch-Based Storage Controller
File System Integration into Data Mining Model
Encoding-Aware Data Routing
Devices and Methods for Providing Port Matching Features for Usb-C Cables and Ports
Adaptive Automated Alarm Response System
Connector for an Electronic Device Having a Grid of Connection Points
Solid-State Device with Multi-Tier Extreme Thermal Throttling
History-Based Prediction Modeling of Solid-State Device Temperature
Stream Oriented Writing for Improving Sequential Write and Read Performance
Solid-State Device with Multiple Thermal Power States
Analyses of Surface-Mount-Technology Components Using Fluorescent-Dye Penetrants
Patent:
11,788,964 →
Application:
17/741,422 →
Self-Aligning Heat Fins for Thermal Management
Indexless Logical-to-Physical Translation Table
Linked XOR Flash Data Protection Scheme
Host Data Stream Assignment With Space-Leveling Across Storage Block Containers
Variable Capacity Zone Namespace (Zns) Flash Storage Data Path
Read Fused Groups with Uniform Resource Allocation
Recognition and Report of Expected Write Amplification Violation
Lead finger for printed circuit board
Site-Based Calibration of Object Detection Rules
Usage-Based Assessment for Surveillance Storage Configuration
Hybrid Terabytes Written (Tbw) Storage Systems
Surface Mount Technology Method and Magnetic Carrier System
Generalized Verification Scheme For Safe Metadata Modification
Multiple Indirection Sizes For Logical-to-Physical Translation Tables
Data Storage Device and Method for Host Multi-Command Queue Grouping Based on Write-Size Alignment in a Multi-Queue-Depth Environment
Memory Die Management
Storage Device Energy Recycling and Cooling
Semiconductor Device Including Embedded Memory Dies and Method of Making Same
Application:
17/746,104 →
Publication:
US 2023/0411340
Avoiding Ungraceful Shutdowns in Storage Devices
Accelerated Cooling in Storage Devices
Mapping for Multi-State Programming of Memory Devices
Alignment Optimization Of Key Value Pair Data Storage
Semi And Cached TLP Coalescing
Key Value Data Placement According To Expected Reads
Thermal Management of Storage Devices Increasing Host Write Performance
Integrated Circuit Chip Storage Container
Flip Chip Bump With Multi-PI Opening
Dynamic Write Shaping
Die Separation Ring for Wafers Having a Large Die Aspect Ratio
Hot-Cold Chunks Soft-Prediction During Programming
Back Pattern Counter Measure for Solid State Drives
Apparatus and Methods for Programming Memory Cells
Data Storage Device and Method for Device-Initiated Hibernation
Storage System and Method for Hybrid Mapping
Proactive Loss Notification and Handling in Data Storage Devices
Magnetoresistive Memory Device Including a Magnetoresistance Amplification Layer
Data Retention (Dr) Warning System
Storage System and Method for Avoiding Header to Improve Parity
Data Storage Device with Multi-Commands
Variable Length ECC Code According To Data Entropy In NVMe Key Value Pair Devices
Systems and Methods of Improved Modular Inversion with Digital Signatures
Storage System and Method for Using a Queue Monitor in a Block Allocation Process
Data Storage Device and Method for Lane Detection and Configuration
Data Storage Device and Method for Lane Selection Based on Thermal Conditions
Storage System and Method for Early Command Cancelation
Workload Triggered Dynamic Capture in Surveillance Systems
Patent:
11,736,796 →
Application:
17/829,479 →
Read Look Ahead Based On Key Analysis In Key Value Data Storage Devices
Mechanical Support for a Tall Offset Die Stack
Application:
17/829,719 →
Publication:
US 2023/0395446
Storage System and Method for Enabling a Software-Defined Dynamic Storage Response
Host Load Based Dynamic Storage System for Configuration for Increased Performance
Semiconductor Device Including Select Dies of Known Thicknesses
Application:
17/831,810 →
Publication:
US 2023/0395438
Semiconductor Device Including Through-Package Debug Features
Data Storage Device and Method for Host Buffer Management
Multiple Sets of Trim Parameters
Method and System for Improving Word Line Data Retention for Memory Blocks
Laser Cutting With Electron Removal
Application:
17/837,175 →
Publication:
US 2023/0411179
Open Block Boundary Group Programming for Non-Volatile Memory
Local Data Compaction for Integrated Memory Assembly
Storage System and Method for Inference of Read Thresholds Based on Memory Parameters and Conditions
Dicing and Wafer Thinning to Form Semiconductor Dies
Data Storage Device and Method for Dynamic Prediction of Random Read with Low Memory Consumption
Data Storage Device with Dynamic Mapping of Low-Density Parity Check (Ldpc) Engines
Data Storage Device and Method for Enabling Metadata-Based Seek Points for Media Access
Preservation of Volatile Data in Distress Mode
Application:
17/839,712 →
Publication:
US 2023/0400988
Peer Storage Device Messaging for Vulnerability Management
Proactive Storage Operation Management Using Thermal States
Proactively Biasing Parameters of Data Storage Device Based on Spatial Position in Storage Enclosure
Semiconductor Device Including Reinforcing Blocks at One or More Mechanical Stress Points
Application:
17/840,322 →
Publication:
US 2023/0402361
Semiconductor Wafer Thinned by Horizontal Stealth Lasing
Scratchpad Cache for Gaming and Iot Hosts
Interface Bus Speed Optimization
Active Time-Based Command Prioritization in Data Storage Devices
Data Mapping Comparison For Improved Synchronization In Data Storage Devices
Key Value Data Storage Device With Tiers
Data Storage Device With Weak Bits Handling
Key Value Data Storage Device With Improved Utilization For Short Key Value Pairs
Pre-Fetch of Data Using Seek Intervals
Deduplication for Data Transfers to Portable Storage Devices
Data Integrity Protection With Partial Updates
Patent:
11,681,581 →
Application:
17/845,770 →
Data Storage Device and Method for Multi-Level Conditional Prediction of Future Random Read Commands
Non-Volatile Memory Die with Latch-Based Multiply-Accumulate Components
Data Storage Device with Noise Injection
Optimized Read-Modify-Writes During Relocation of Overlapping Logical Blocks
Data Storage Device with Noise Injection
Memory Device with Latch-Based Neural Network Weight Parity Detection and Trimming
Non-Volatile Memory Die with Bit-Flip Object Insertion
Systems And Methods With Variable Size Super Blocks In Zoned Namespace Devices
Proactive Hardening of Data Storage System
Memory Partitioned Data Storage Device
Security Indicator on a Data Storage Device
Storage Media Based Search Function For Key Value Data Storage Devices
Key-To-Physical Table Optimization For Key Value Data Storage Devices
Data Storage Device Management System
Host Assisted Application Grouping for Efficient Utilization of Device Resources
Patent:
11,797,183 →
Application:
17/850,787 →
Integrated Circuit Test Socket with Integrated Device Picking Mechanism
Configuration of New Storage Devices in a Storage Device Pool
Application:
17/851,566 →
Publication:
US 2023/0418486
Detection and Isolation of Faulty Holdup Capacitors Using Hardware Circuit in Data Storage Devices
Non-Volatile Memory with Precise Programming
Wireless Device Loss Prevention and Discovery
Power Management for Wireless Device Loss Prevention and Discovery
Application:
17/852,301 →
Publication:
US 2023/0422171
Asynchronous Operation Completion Notification
Automatic Data Erase from Data Storage Device
Transfer of Internal Device Data Over Command Response
Peer-to-Peer Data Transfer for Video on Demand from an Edge Data Storage Device to a Browser
Redundant Video Storage Among Networked Video Cameras
Patent:
11,741,804 →
Application:
17/852,707 →
Video Surveillance Systems Using Out of Band Key Exchange
Audio Sensors for Controlling Surveillance Video Data Capture
Failed Temperature Sensor Detection and Mitigation Within Data Storage Devices
Performance Indicator on a Data Storage Device
Data Storage Device and Method for Adaptive Host Memory Buffer Allocation Based on Virtual Function Prioritization
Just-In-Time Re-Partitioning of Feature Maps for Efficient Balancing of Compute Core Workloads
Storage System and Method for Proactive Die Retirement by Fatal Wordline Leakage Detection
LBNs Prefetching Per CPU
Controller for Quality Of Service Based Arbitrations
Cache Write Overlap Handling
Controller for Quality Of Service Based Arbitrations
Data Parking for ZNS Devices
Storage System and Method for Data Placement in Zoned Storage
Shared Vias for Differential Pair Trace Routing
Patent:
11,832,383 →
Application:
17/864,101 →
Multi-Stage Data Compaction in Nand
Management of Host File-System Defragmentation in a Data Storage Device
Logical-To-Physical Mapping for Defragmentation of Host File System in a Data Storage Device
Fast Garbage Collection in Zoned Namespaces Ssds
Accelerated Encryption During Power Loss
Creating and Using Delta L2P Entries
Delta L2P Entry Usage
System and Method for Depositing Underfill Material
Memory Controller for Resolving String to String Shorts
Storage System and Method for Optimizing Host-Activated Defragmentation and Proactive Garbage Collection Processes
Determine Link Startup Sequence (LSS) Type Using Reference Clock Frequency And Attribute
Decoupled External Storage Device Booting
Content-Rich Error Notification
Identified Zones For Optimal Parity Sharing Zones
Storage System and Method for Using Read and Write Buffers in a Memory
Efficient Sub-Block Erasing
Application:
17/878,490 →
Publication:
US 2024/0036729
Managing Overwrite Data Within Solid State Drives
Adaptive Context Metadata Message for Optimized Two-Chip Performance
Write Coalescing via Hmb to Optimize Write Performance
Data Storage Device That Detects And Releases Bottlenecks
Stress Test for Grown Bad Blocks
Fast Search for Leaky Word Line
NVMe Boot Partition Error Correction Code Enhancement
Bifacial Semiconductor Wafer
POWER TARGET CALIBRATION FOR CONTROLLING DRIVE-TO-DRIVE PERFORMANCE VARIATIONS IN SOLID STATE DRIVES (SSDs)
Open Block Relocation
Non-Volatile Memory Die with on-Chip Data Augmentation Components for Use with Machine Learning
Application:
17/897,028 →
Publication:
US 2022/0405532
Storage Controller Having Data Augmentation Components for Use with Non-Volatile Memory Die
Adaptive Host Memory Buffer Traffic Control Based On Real Time Feedback
Storage System and Method for Implementation of Symmetric Tree Models for Read Threshold Calibration
Data Retention Management After Power Off
Compaction of a Logical-to-Physical Table for Zoned Namespace Nonvolatile Memory
Address Translation for Zoned Namespace Nonvolatile Memory Using a Compacted Logical-to-Physical Table
System and Method for Retrimming Removable Storage Devices
Handling Write Data Burst for Improved Performance and Resource Usage
Data Storage Device and Method for Power on Reset and Read Error Handling
Thermoelectric Semiconductor Device and Method of Making Same
Metadata Management In Key Value Data Storage Device
Asymmetric Time Division Peak Power Management (TD-PPM) Timing Windows
Data Recovery for Zoned Namespace Devices
Thermal Measurement of Materials
Optimization of Non-Aligned Host Writes
Nand Die with Rdl for Altered Bond Wire Bandwidth in Memory Devices
Ssd Use of Host Memory Buffer for Improved Performance
Hybrid Logical to Physical Mapping for Zns Based Ssds
Toggle Mode Interface for Data Integrity Protection
Adaptive Tuning of Memory Device Clock Rates Based on Dynamic Parameters
Nand Early Erase Termination Based on Leakage Current Test
Predictive Performance Indicator for Storage Devices
Accelerator Queue in Data Storage Device
Splitting Sequential Read Commands
Parallel Fragmented Sgl Fetching for Hiding Host Turnaround Time
Efficient L2P Dram for High-Capacity Drives
Predicting an Unsuccessful Error Correction Code Condition Using a Dynamic Read Threashold Table
Block Layer Persistent Memory Buffer
Application:
17/946,541 →
Publication:
US 2024/0094950
Dynamic Ordering of Memory Die Programming in a Metablock
Exception Handling Using Security Subsystem in Storage Device
Identification and Classification of Write Stream Priority
Dynamic TD-PPM State And Die Mapping In Multi-NAND Channels
Patent:
11,893,253 →
Application:
17/949,127 →
Partial Speed Changes to Improve in-Order Transfer
Patent:
11,838,033 →
Application:
17/949,130 →
Dynamic And Shared CMB And HMB Allocation
NVMe Copy Command Acceleration
Effective Key Management for Data Encryption and Decryption
Application:
17/950,593 →
Publication:
US 2023/0019584
Unaligned Deallocated Logical Blocks Datapath Support
Automated Fast Path Processing
Color Changing Storage Device Housing
Control Table Set Determination In Storage Devices
Configurable Capacitors with 3D Non-Volatile Array
Priority-Based Data Movement
AER and AEN for Overlapping Cross Feature
Finding and Releasing Trapped Memory in Ulayer
Data Storage with Improved Cache Read
Non-Planar Antennas for Portable Storage Devices
Hmb Multi-Segment Optimal Selection
Control Table Set Management In Storage Devices
Application:
17/958,185 →
Publication:
US 2024/0111455
Data Storage Device That Detects and Releases Bottlenecks In Hardware
Data Storage Device That Detects And Releases Input Queue Bottlenecks
Overhead Reduction in Data Transfer Protocol for NAND Memory
Modified Distribution of Memory Device States
Data Storage Device with Flow Tracking Ability
Apparatus and Method for Regulating Available Storage of a Data Storage System
Dynamic Valley Searching in Solid State Drives
Continuous Nand Data-Transfer with Dynamic Tm
Application:
17/965,168 →
Publication:
US 2023/0105936
Advanced Ultra Low Power Error Correcting Code Encoders and Decoders
Patent:
11,838,032 →
Application:
17/968,249 →
Storage Device for Storing Model Checkpoints of Recommendation Deep-Learning Models
Toggle Mode (TM) Coding With Circuit Bounded Array Memory
Command Draining Using Host Memory Buffer
Hinting Mechanism for Efficient Accelerator Services
Application:
18/053,644 →
Publication:
US 2023/0236969
Voltage Controlled Magnetic Anisotropy (Vcma) Memory Devices Including Platinum Containing Layer in Contact with Free Layer
Memory Device Using CbA Technology
NVMe CONTROLLER MEMORY MANAGER PROVIDING CMB CAPABILITY
Data Integrity Protection Of SSDs Utilizing Streams
Motion Vector Determination with CMOS
Application:
18/104,176 →
Publication:
US 2023/0179777
Solid State Drive Cache Eviction Policy by an Unsupervised Reinforcement Learning Scheme
Virtual Block Pools For Protecting Device Health
Semiconductor Wafer Thinned by Stealth Lasing
Direct Host Access to Storage Device Memory Space
Application:
18/139,912 →
Publication:
US 2024/0078188
Self-Aware Cryptocurrency Wallets
Data Storage Device Adaptor with Securement Mechanism
Optimizing Chia Plotting Storage and Memory Space
Application:
18/160,974 →
Publication:
US 2023/0280914
Management of Storage Devices Utilizing Non-Fungible Tokens
Application:
18/161,209 →
Publication:
US 2023/0350980
Embedded PHY (EPHY) IP Core for FPGA
System and Method for Utilizing a Data Storage Device with Power Performance Profiles and/or Temperature Monitoring
Data Storage Device and Method for Intelligent Block Allocation
Data Storage With Optimized Boot Files Loading
QoS Optimization By Using Data Tracking Module
Write Completion Pacing For Unbalanced Command Length
Light-Weight BES Approximation
Delayed XOR Rebuild With Priority In Multi-Protocol Products
Optimization Of An Active Range Of mSets Stored In A Compressed Address Table
UECC Block Mapping Update To A Bad Block
Low Power Optimization Based Upon Host Exit Latency
Flash Interface With Switching Logic
Multi-Tenant Device Read Command Service Balancing
SSD Content Preloading Via Broadcasting System
Application:
18/218,874 →
Publication:
US 2024/0419331
Statistically Driven Run Level Firmware Migration
Application:
18/218,876 →
Publication:
US 2024/0361911
Data Integrity in Key Value Solid-State Drives
Enhanced End To End System Failure Recovery
Pre-Emptive Operations For Faster XOR Recovery And Relocation
Data Storage Device and Method for Swap Defragmentation
Storage System and Method for Circuit-Bounded-Array-Based Time and Temperature Tag Management and Inference of Read Thresholds
Data Storage Device and Method for Reducing Flush Latency
Data Storage Device and Method for Reducing Read Disturbs When Reading Redundantly-Stored Data
Semiconductor Device Including Vertically Interconnected Semiconductor Dies
Application:
18/221,497 →
Publication:
US 2024/0120317
Data Storage Device and Method for Handling Write Commands in Zoned Storage
Data Storage Device and Method for Using Zones of Memory in a Read Scrub Operation
System and Method for Die Crack Detection in Wafer-to-Wafer Bonding
Application:
18/222,057 →
Publication:
US 2024/0249984
Ball Grid Array Semiconductor Device with Thermal Pads and Printed Circuit Board Therefor
Application:
18/222,362 →
Publication:
US 2024/0162106
Tsv Semiconductor Device Including Inductive Compensation Loops
Application:
18/222,632 →
Publication:
US 2024/0213151
Stacked Chip Scale Semiconductor Device
Application:
18/222,646 →
Publication:
US 2024/0243101
Semiconductor Storage Device Including Staggered Semiconductor Memory Devices on Opposed Surfaces
Semiconductor Storage Device Including Pcb Edge Heat Dissipation
Application:
18/222,776 →
Publication:
US 2024/0260237
Adaptive Erase Scheme for a Memory Device
Rapid Installation Screw with Radially Expanding Threads
Application:
18/222,859 →
Publication:
US 2024/0337282
Multiple Stage Fuse Circuitry for Counting Failure Events
Data Storage Device and Method for Enhanced Recovery Through a Hardware Reset of One of Its Discrete Components
Data Storage Device and Method for Host-Assisted Improved Error Recovery Using a Correlation Factor
Data Storage Device and Method for Host-Assisted Efficient Handling of Multiple Versions of Data
Data Storage Device and Method for Dynamic Controller Memory Buffer Allocation
Data Storage Device and Method for Race-Based Data Access in a Multiple Host Memory Buffer System
Generation of Quick Pass Write Biases in a Memory Device
Data Storage Device and Method for Hiding Tweak Generation Latency
Data Storage Device and Method for Releasing a Source Block Having an Uncorrectable Error
Data Storage Device and Method for Runtime Exclusive-Or Zoning During Folding
Data Storage Device and Method for Read Scrub with Reduced Read Amplification
Data Storage Device and Method for Host-Assisted Deferred Defragmentation and System Handling
Intermediate Re-Verify for Achieving Tighter Threshold Voltage Distributions in a Memory Device
Highly Efficient SSD Power Management Through PCIe Data Rate Modulation
Systems and Methods for Performing Independent Plane Concurrent Memory Operations in Non-Volatile Memory Structures
Application:
18/224,202 →
Publication:
US 2024/0296882
Ssd System with Consistent Read Performance
Data Storage Device and Method for Dynamic Logical Page Write Ordering
Data Storage Device and Method for Selecting a Data Recovery Mechanism Based on a Video Frame Position
Data Storage Device and Method for Scanning Memory Blocks
Data Storage Device and Method for Logical Range Lock
On-Chip Performance Throttling
Programming Erase State as Last Program State During a Programming Cycle of a Non-Volatile Memory Structure
Application:
18/225,315 →
Publication:
US 2024/0290390
Fast Look Ahead Read for Non-Volatile Memory by Removing Pre-Read Redundancy
Variable Read Method for Read Time Performance Improvement of Non-Volatile Memory
Single-Level Cell Pump Skip Program Operation Preliminary Period Timing Optimization for Non-Volatile Memory
Loop Dependent Bit Line and Read Biases in a Memory Device
Data Storage Device and Method for Optimized Refresh
Data Storage Device and Method for Improving Asynchronous Independent Plane Read (AIPR) Utilization
Data Storage Device with Balanced Background Operations and Method Therefor
Data Storage Device and Method for Performance-Dependent Storage of Parity Information
Focused Testing and Verification of Circuit Designs Using Hardware Description Language Simulation
Application:
18/226,199 →
Publication:
US 2024/0184967
Test Controller Enabling a Snapshot Restore and Resume Operation Within a Device Under Test
Data Storage Device and Method for Performing an Action on an Area of Memory to Satisfy a Host-Provided Target Operating Condition
Data Storage Device and Method for Predictable Low-Latency in a Time-Sensitive Environment
Data Storage Device and Method for Host-Controlled Data Compression
Regular Transistor Threshold Voltage Refresh for Semi-Circle Drain Side Select Gates
Save Mode for Erase Verify Skipping to Reduce Power Consumption in Erase Operation
Application:
18/226,673 →
Publication:
US 2024/0385766
Full Sequence Program for Edge Word Line Quad-Level Memory Cells
Application:
18/227,175 →
Publication:
US 2024/0363167
Data Storage Device and Method for Time-Pooled Hot Data Relocation
Data Storage Device and Method for Providing External-Interrupt-Based Customized Behavior
Removable Memory Card with Efficient Card Lock Mechanism, XY Ratios, and Pads Layout
Binary Read-Based Fast Algorithm for Optimal Read Level Acquisition
Unselect Word Line Switch Bias Scheme for Non-Volatile Memory Apparatus
Reconfigurable Lines in Different Sub-Block Modes in a Nand Memory Device
Positive Sensing in Low Power Operation Mode in a Memory Device
Asymmetric Vreadk to Reduce Neighboring Word Line Interference in a Memory Device
Read Access Management of Host Performance Booster (Hpb) Regions by a Storage Device
Read Only Mode Handling in Storage Devices
Patent:
12,124,708 →
Application:
18/228,806 →
Word Line Dependent Word Line Switch Design and Programming Techniques
Hybrid Erase for Data Retention Threshold Voltage Margin Improvement
Application:
18/229,257 →
Publication:
US 2024/0386973
Program Verify Word Line Ramping Delay for Lower Current Consumption Mode
Adaptive Single-Side Erase to Improve Cell Reliability
Memory Device Including Hafnium or Zirconium Oxide Containing Blocking Dielectric and Tungsten Nitride Barrier and Methods of Forming the Same
Application:
18/229,489 →
Publication:
US 2025/0048641
Read Power Savings by Temporarily Disabling Bitline Voltage
Optimized Read Current Consumption Based on Lower Page Read Information for Non-Volatile Memory Apparatus
Automatic Bit Line Voltage and Bit Line Voltage Temperature Compensation Adjustment for Non-Volatile Memory Apparatus Current Consumption Reduction
Systems and Methods to Avoid Over Programming at Infrequent Smart Verify Acquisition for High-Performance 3D Nand
Smart Early Program Termination Algorithm for Neighbor Plane Disturb Countermeasure
Enabling Significant Scaling of Wordline Switch with Wordline Dependent Negative Bitline Voltage
Solid-State Drive Secure Data Wiping for Reuse and Recycling
Open Block Detection Method Using for First and Second Time Period Read Time Valley for Non-Volatile Memory Apparatus
Application:
18/230,270 →
Publication:
US 2024/0420775
Plane and Block Location Dependent Voltage Biases in Nand Memory
Channel Pre-Charge Process for Memory Devices Using Hole Pre-Charge Operation
Lower Vread for Erased Word Lines in Post-Write Dummy Reads
Application:
18/230,379 →
Publication:
US 2024/0385769
Computational Storage Device with Computation Precision-Defined Fixed Point Data Grouping and Storage Management
Application:
18/230,576 →
Publication:
US 2025/0004661
Access-Controlled Delivery of Content to Network Attached Storage
Stop Read Go Settings for Low Suspend Latency Applications
Application:
18/230,832 →
Publication:
US 2024/0428834
Analog Bitscan Techniques in a Memory Device
Application:
18/230,972 →
Publication:
US 2025/0006277
Data Storage Device and Method for Identifying a Failing Area of Memory Based on a Cluster of Bit Errors
State-Dependent Fail Bit Count Criteria for Memory Apparatus Program Performance Gain
Application:
18/231,368 →
Publication:
US 2025/0054556
In Situ Data Refresh Without Erase/Program Cycles
Application:
18/231,395 →
Publication:
US 2024/0363178
Erase Techniques Using Analog Bitscan in a Memory Device
Application:
18/231,629 →
Publication:
US 2025/0006278
Privacy-Preserving Distributed Computing
Application:
18/231,706 →
Publication:
US 2024/0146700
Evaluating Convolutions Using Encrypted Data
Application:
18/231,716 →
Publication:
US 2024/0171372
Storage Devices Having Multi-Channel Capacitive Sensors for Detecting Gesture Based Commands
Memory Prefetch Based on Machine Learning
Five Level Cell Program Algorithm with Appended Bit Level Erase for Additional Threshold Voltage Budget
Application:
18/232,010 →
Publication:
US 2025/0054555
Proactive Caching of Data for Accelerator Cores in a Storage Device
Protocol for Solid State Drive with High Quality of Service
Data Storage Device Configured for Use with a Generative-Adversarial-Network (Gan)
Programming Techniques That Utilize Analog Bitscan in a Memory Device
Data Storage Device Configured for Use with a Generative-Adversarial-Network (Gan)
Host-Independent Format Operation of Usb-Based Storage Devices
Host-Independent Disk Optimization and Data Operations for Usb-Based Storage Devices
Smart Card with Bus Interface Receptacle Printed as Part of Pcb
Single Block Mode Block Handling for Single-Side Gidl Erase
Vpass Auto Layer Compensation in a Memory Device
Data Storage Device Configured for Use with a Generative-Adversarial-Network (Gan)
Asymmetric Pass Voltage Scheme for Non-Volatile Memory Apparatus Size Reduction
Application:
18/233,640 →
Publication:
US 2025/0006244
Three-Dimensional Memory Device Including a Metal Oxide Etch Stop Layer and Methods for Forming the Same
Application:
18/233,697 →
Publication:
US 2023/0389317
Three-Dimensional Memory Device with Layer Contact via Structures Located in a Memory Array Region and Methods of Forming the Same
Application:
18/233,759 →
Publication:
US 2024/0381639
Managing Data Descriptor Reads During Command Processing in a Storage Device
Application:
18/233,970 →
Publication:
US 2024/0329881
Securely Erasing Data on Inoperative Storage Device
Application:
18/233,981 →
Publication:
US 2024/0320110
Programming Techniques That Utilize Analog Bitscan in a Memory Device
Application:
18/234,094 →
Publication:
US 2025/0006279
Energy Efficient Fast Read in a Memory Device
Memory Device with Multiple Plane Functionalities
Smart Verify Algorithm for Improving Reliability for Ultra High-Performance 3D Nand
Thermal Recovery in Multi-Protocol Devices
Error Handling in Key-Value Solid State Drives
Free Space Management in Storage Devices Having Non-Uniform-Sized Memory Blocks
Efficient Usage of Redundant Columns in Flash Memory
Error Handling in Asymmetric Sub-Blocks
Application:
18/237,041 →
Publication:
US 2024/0354007
Reclaim Package Cache for Thermal Throttling
Method for Optimizing Logical-to-Physical Table Updates for Fixed Granularity Logical-to-Physical Tables
Application:
18/237,301 →
Publication:
US 2024/0370368
Interposer for Troubleshooting a Ball Grid Array (Bga) Device and Coupling the Bga Device to a Printed Circuit Board with Limited Heat Exposure
Application:
18/238,952 →
Publication:
US 2025/0081357
Data Storage Device and Method for Inferring a Read Threshold Using a Time Tag Determination
Data Storage Device and Method for Predicting Future Read Thresholds
Optimized Erratic Program Detection Process
Programming Techniques to Improve Erase State Upper Tails in a Memory Device
Efficient Logical to Physical Mapping Updates
Low Power State Staging
Three-Dimensional Memory Device Including Backside Semiconductor Source Structure and Methods for Forming the Same
Application:
18/343,118 →
Publication:
US 2025/0008736
Three-Dimensional Memory Device Including Backside Semiconductor Source Structure and Methods for Forming the Same
Application:
18/343,162 →
Publication:
US 2025/0008729
Reducing Data Communications in Distributed Inference Schemes
Application:
18/343,173 →
Publication:
US 2024/0095540
Memory Device Including Aluminum Nitride Diffusion Barrier Layer and Methods for Forming the Same
Application:
18/344,227 →
Publication:
US 2025/0008730
Mounting of Capacitors on Printed Circuit Boards for Non-Volatile Memory Devices
Folding Ordering Scheme for Improved Throughput in Non-Volatile Memory
Adaptive Word Line Stress for Leak Detection in Non-Volatile Memory
Non-Volatile Memory with Layout Adaptive Problematic Word Line Detection
Method of Making a Three-Dimensional Memory Device Using Composite Hard Masks for Formation of Deep via Openings
Application:
18/346,520 →
Publication:
US 2023/0343641
Three-Dimensional Memory Device Including Discrete Charge Storage Elements and Methods of Making Thereof
Application:
18/347,371 →
Publication:
US 2023/0345727
Semiconductor Device Including Metal Interconnect Structures That Contain Selectively-Grown Dielectric Spacers and Methods for Forming the Same
Application:
18/347,404 →
Publication:
US 2023/0352401
Read Collision Avoidance in Sequential Mixed Workloads
Hold-Up Capacitor Failure Handling in Data Storage Devices
Annular Structure for an Electronic Flame Off Wand
Application:
18/348,483 →
Publication:
US 2025/0015040
ZONE-BASED GARBAGE COLLECTION IN ZNS SSDs
System Recovery During Cgi-Wl Defect
Victim Zone Selection for Zone Compaction During Garbage Collection in Zns Devices
Circuit Failure Protection
Excess Cmb Utilization by Storage Controller
Three-Dimensional Memory Device Including Horizontal Semiconductor Channels and Methods of Forming the Same
Application:
18/349,488 →
Publication:
US 2025/0024672
Three-Dimensional Memory Device Having Controlled Lateral Isolation Trench Depth and Methods of Forming the Same
Three-Dimensional Memory Device Having Controlled Lateral Isolation Trench Depth and Methods of Forming the Same
Application:
18/349,560 →
Publication:
US 2025/0024681
I/O Modulation Scheme for Ultra-High Data Throughput with Massive Nand Parallelism
Key Version Management in Storage Devices
Optimized Ssd for Game Loading and Rendering
SSD with Reference Clock Loss Tolerant Oscillator
Fast Execution of Barrier Command
Scatter Gather List Adaptive Bucketing
Bandwidth Balancing for a Single Namespace Tenant in Multi-Function Nonvolatile Memory Express Devices
Data Storage with Low Cost Dies
Handling Data Storage Device Failure Using Remote System
Retrimming Removable Storage Device Using Host System
Failure Recovery Using Command History Buffer in Storage Device
Folding Zone Management Optimization in Storage Device
Efficient Deallocation and Reset of Zones in Storage Device
Application:
18/352,162 →
Publication:
US 2024/0168684
Stream Data Management in Storage Device Using Defragmentation
Optimized Predictive Loading in Storage Device
Enhanced Read Cache for Stream Switching in Storage Device
Adaptive Use of Multiple Channels in a Storage Device
Authentication of Sanitize Erase
Patent:
12,175,114 →
Application:
18/353,860 →
Hiberate (HIB8) Exit Time for Universal Flash Storage (Ufs) Devices by Monitoring When to Enable or Disable Low Power States Without Waiting on Squelch Detection
Write Buffer Linking for Easy Cache Reads
Offloading Data Storage Device Processing Tasks to a Graphics Processing Unit
Application:
18/354,150 →
Publication:
US 2024/0134696
Using Internal Operation Files Having Known Patterns Across Multiple Devices
Application:
18/354,174 →
Publication:
US 2025/0028481
Electrostatic Discharge Detection and Data Storage Device Reaction
Simulating Multi-Sensor Environment for Thermal Throttling in Storage Device
Illusory Free Data Storage Space in Data Storage Devices
Zns Protection with Small Slc Cache Using Zone Groups
Dynamic Zone Group Creation and Recalibration Balancing
Enhanced Read Retry (Err) for Data Recovery in Flash Memory
Application:
18/355,090 →
Publication:
US 2024/0304273
Key-Per-Io Multiple Tenant Isolation
De-Fragmentation Acceleration Using Overlap Table
Nand Die with Wire-Bond Inductive Compensation for Altered Bond Wire Bandwidth in Memory Devices
Application:
18/355,111 →
Publication:
US 2024/0145424
Efficient Consolidation for Two Layer Ftl
Multi-Time Programmable Memory Devices and Methods
Application:
18/355,359 →
Publication:
US 2024/0379142
Dual Reference Zq Calibration Circuits and Methods
Apparatus and Method for Two-Step Read of Resistive Random Access Memory
Secured Failover Access Through Data Storage Device Side Channels
Systems and Methods for Improving Find Last Good Page Processing in Memory Devices
Sub-Block Mode (Sbm) Pre-Charge Operation Sequences
Fast Direct Look Ahead Read Mode in a Memory Device
Word Line Layer Dependent Stress and Screen Voltage
Memory Device and Method of Assembling Same
Application:
18/356,838 →
Publication:
US 2024/0194560
Generating a Random Number Using a Non-Volatile Memory Based Physical Uncloneable Function
Application:
18/357,208 →
Publication:
US 2024/0249757
High Thermal Dissipation Features for a Flip Chip Structure
Application:
18/357,211 →
Publication:
US 2024/0304515
Semiconductor Chip Having a High Thermal Liquid Coolant
Application:
18/357,341 →
Publication:
US 2024/0304518
Non-Volatile Memory That Dynamically Reduces the Number of Bits of Data Stored Per Memory Cell
Solder Barrier Contact for an Integrated Circuit
Application:
18/357,379 →
Publication:
US 2024/0324109
Substrate Having an Increased Metal Trace Thickness
Application:
18/357,728 →
Publication:
US 2024/0332156
Slow Programming on Weak Word Lines of a Memory Device
Commands Splitting Based on Flat Logical Block Address and Security Key
Recovery of Retired Memory Blocks in a Memory Device
Reordering Commands to Optimize Execution of the Commands
Shock Absorber Assembly for a Printed Circuit Board
Application:
18/357,759 →
Publication:
US 2024/0381524
Optimized Power Up in Storage Memory Devices
Three-Dimensional Memory Device Containing Trench Support Bridge Structures and Methods for Manufacturing the Same
Application:
18/357,781 →
Publication:
US 2024/0371789
Partial Die Blocks
Transparent Host Memory Buffer
Temperature Dependent Refresh Read Rate
Statistics Based Non-Volatile Memory Health Mitigation
Data Integrity Check in Non-Volatile Storage
High Voltage Field Effect Transistors with Different Sidewall Spacer Configurations and Method of Making the Same
Application:
18/358,633 →
Publication:
US 2025/0040239
Post-Program Erase in 3D Nand
Application:
18/358,635 →
Publication:
US 2024/0296891
Non-Volatile Memory with Intelligent Erase Testing to Avoid Neighbor Plane Disturb
Application:
18/358,651 →
Publication:
US 2024/0312538
High Voltage Field Effect Transistors with Different Sidewall Spacer Configurations and Method of Making the Same
Estimating Peak Source Current Using Memory Die Substrate Temperature Detection
Cross-Point Ovonic Frustum Memory Device and Method of Making the Same
Application:
18/358,768 →
Publication:
US 2025/0040150
Distributed Temperature Sensing Scheme to Suppress Peak Icc in Non-Volatile Memories
Processing Commands in a Sequential Write Required Zone Model
Notifications for Avoiding Thermal Shutdown
Application:
18/359,144 →
Publication:
US 2024/0231962
Ml Assisted Dynamic Decoding Gear Selection
Data Padding Reduction in Log Copy
Application:
18/359,151 →
Publication:
US 2024/0272794
Cmb Caching Using Hybrid Sram/Dram Data Path
Enhanced End to End Protection in Key Value Storage Devices
Reverse Garbage Collection Process for a Storage Device
Bypass Buffer for Worn Out Codewords
Multiple Circuit Board Assembly Including a Support Element and Method of Manufacture Thereof
Error Handling During a Memory Compaction Process
Application:
18/359,637 →
Publication:
US 2024/0386984
Thermally Conductive Spacer
Application:
18/359,645 →
Publication:
US 2024/0404994
Ensuring Quality of Service in Multi-Tenant Environment Using Sgls
Application:
18/359,674 →
Publication:
US 2024/0168801
Ats Pri Support with Implicit Cache
Firmware Scheme for 3 Tier Memories
Avoiding Garbage Collection in Media Storage Devices
Non-Volatile Memory with Secure Erase
Non-Volatile Memory with Early Ramp for Improved Performance
Non-Volatile Memory with Sub-Block Erase
Application:
18/359,829 →
Publication:
US 2024/0395332
Erase Saturation Mitigation in Non-Volatile Memory
Application:
18/360,075 →
Publication:
US 2024/0379175
Multi-Step Read Pass Voltage Discharge for Icc Reduction
Printed Circuit Board Having a Temperature Profiling Connection Pad
Memory Controller Support for Mixed Read
Current Source for Read of Programmable Resistance Memory Cells
Multi-Plane High Density Connector
Application:
18/360,167 →
Publication:
US 2024/0396240
Bond Wire Having a Recycled Thermoplastic Core with Conductive Fillers
Application:
18/360,361 →
Publication:
US 2024/0404980
Error Rate Management in Non-Uniform Memory Arrays
Application:
18/360,398 →
Publication:
US 2024/0403163
Dynamic Bitscan for Non-Volatile Memory
Evolving Bad Block Detection in Non-Volatile Memory
Memory Controller with Common Request Buffer
Semiconductor Die Stacking Architecture and Connection Method Therefore
Application:
18/360,555 →
Publication:
US 2025/0006701
System and Method for Valid Window Maximization in Toggle Mode Link Using Systematic Skew Addition to Compensate for Sso and Crosstalk
Electrically Coupling Printed Circuit Boards Using a Snap-Fit Connector
Electrolytic Capacitors Having Enclosures That Enable the Capacitors to Be Surface Mounted to a Substrate
Application:
18/361,061 →
Publication:
US 2024/0407100
Snap Fit Bracket for Electrolytic Capacitors
Single Package Data Storage Device
Application:
18/361,081 →
Publication:
US 2024/0407180
Dynamically Determining a Memory Block Threshold for Initiating a Garbage Collection Process
Semiconductor Device Package with Coupled Substrates
Application:
18/361,118 →
Publication:
US 2024/0203851
System and Method for Measuring Thermal Performance of Substrates used in Semiconductor Device Assembly
Application:
18/361,129 →
Publication:
US 2024/0222168
Multi-Chip Package with Detachable Chips
Application:
18/361,147 →
Publication:
US 2024/0332110
Semiconductor Device Package with Die Stackup and Interposer
Application:
18/361,168 →
Publication:
US 2024/0312916
Record and Playback Commands for Storage Devices
Identification and Retrieval of Recently-Used Files at an External Storage Device
Three-Dimensional Memory Device Containing Peripheral Circuit with Fin and Planar Field Effect Transistors and Method of Making Thereof
Application:
18/361,550 →
Publication:
US 2024/0371760
Three-Dimensional Memory Device Containing Overlying Thin Film Transistor Control Circuit and Method of Making Thereof
Application:
18/361,575 →
Publication:
US 2024/0387370
Three-Dimensional Memory Device and Method of Making Thereof Using Ion Implanted Etch Stop Layer on a Sacrificial Fill Material
Application:
18/361,594 →
Publication:
US 2024/0371761
Three-Dimensional Memory Device with Through-Stack Contact via with Conductive Fins
Application:
18/361,629 →
Publication:
US 2024/0373631
Irregular Jumbo Block Size Unification
Application:
18/361,642 →
Publication:
US 2024/0319898
Non-Volatile Memory with Multiple Data Resolutions
Non-Volatile Memory with Adjustable Ramp Rate
Non-Volatile Memory with Decline State Operation
Non-Volatile Memory with Sub-Block Programming
Non-Volatile Memory with Neighbor Plane Program Disturb Avoidance
Insulation Layer for a Semiconductor Package
Application:
18/362,128 →
Publication:
US 2024/0413032
Testing Paddle for Semiconductor Device Characterization
Application:
18/362,140 →
Publication:
US 2024/0426904
Vertically Mountable Snap Fit Bracket for Electrolytic Capacitors
Data Receiver Design in Ddr Memory Interfaces
Non-Volatile Memory with High Performance Read
Application:
18/362,509 →
Publication:
US 2025/0046386
Non-Volatile Memory with Concurrent Programming
Three-Dimensional Memory Device with Laterally Separated Source Select Electrodes and Methods of Forming the Same
Multi-Host Bandwidth Management Considering External and Internal Traffic
Shallow Erase for Erase Pool Management
Application:
18/363,470 →
Publication:
US 2025/0046380
Three-Dimensional Memory Device Including a Bit-Line-Bias Vertical Transistor Block and Methods of Operating the Same
Cross-Point Magnetoresistive Memory Array Containing Carbon-Based Layer and Method of Making the Same
Application:
18/363,542 →
Publication:
US 2024/0373648
Predictive Adjustment of Multi-Camera Surveillance Video Data Capture Using Graph Maps
Skipping Completion for Repeat Lbas Based Upon Lba Tracking
Application:
18/364,735 →
Publication:
US 2025/0044986
Predictive Adjustment of Multi-Camera Surveillance Video Data Capture
Data Storage Device Backup
Apparatus and Methods for Increasing Cross Bit Line Pitch in Non-Volatile Memory Control Circuits
Application:
18/365,394 →
Publication:
US 2025/0048637
Simultaneous Lower Tail Verify with Upper Tail Verify
Aborted Operation Detection for Nonvolatile Memory with Non-Uniform Erase
Application:
18/366,213 →
Publication:
US 2024/0428874
Programmable Telemetry and Alerts for Storage Devices
Semiconductor Device Package with Die Stackup and Connection Platform
Application:
18/366,396 →
Publication:
US 2024/0387461
Non-Volatile Memory with Sub-Block Mode and Full Block Mode
Application:
18/366,572 →
Publication:
US 2025/0054550
Bit Line Timing Based Cell Tracking Quick Pass Write for Programming Non-Volatile Memory Apparatuses
Threshold Voltage Budget by Employing an Oxide-Nitride Pitch Dependent Threshold Voltage Window
Application:
18/369,028 →
Publication:
US 2025/0095738
Neighbor Plane Disturb (Npd) Detection for Memory Devices
Word Line Zone Based Unselect Word Line Bias to Enable Single-Side Gate-Induced Drain Leakage Erase
Method for Handling Extreme Temperatures in Storage Devices
Application:
18/372,152 →
Publication:
US 2024/0232070
Method and System for Handling Host Commands Overlapping with Deferred Unmap Address Ranges in Storage Devices
Controlling Input/Output Pad Discharge Rate in Storage Devices
Application:
18/372,777 →
Publication:
US 2025/0105843
Providing Host with Multiple Mapping Information That Span Across Multiple Hpb Regions
Enabling Power Optimization Through Dram Bank Management in Solid State Drives
Application:
18/373,403 →
Publication:
US 2025/0103220
Data Storage Device and Method for Delaying Execution of a Host Write Command to Perform an Internal Memory Operation
Shortened Commands To Reduce Data Transmission
Multiple Command Format Interpretation For SSD
Adaptive Wear-Leveling of Sub-Blocks in Non-Volatile Memory
Application:
18/382,860 →
Publication:
US 2025/0130719
Method for Isolating Faulty Nand Temperature Sensor
Application:
18/383,730 →
Publication:
US 2025/0140330
Partial Speed Changes To Improve In-Order Transfer
Scheme to Fetch Optimal Read Parameters by Skipping Invalid Wordlines
Time Bound Partial Format Operation in a Storage Device
Patent:
12,254,209 →
Application:
18/383,854 →
Word Line Bias During Stripe Erase in a Memory Device
Application:
18/384,204 →
Publication:
US 2025/0140321
Data Processing Methods and Apparatus for Use with Feature Maps in Sparse Convolutional Neural Networks
Application:
18/386,191 →
Publication:
US 2025/0141470
Data Processing Methods and Apparatus for Use with Feature Maps in Sparse Convolutional Neural Networks
Application:
18/386,210 →
Publication:
US 2025/0139415
Host Queues Recovery In Exception Flows
Patent:
12,248,703 →
Application:
18/386,797 →
Data Storage Device and Method for Multiple Meta Die Balancing
Method and Device for Data Storage Device User Authentication
Stuck Bits Encoding and Decoding on a Storage Device
Reducing Read Disturb in a Semi-Circular Memory Cell of a Memory Device
State Dependent Suspend-Resume-Go for Performance Improvement in a Memory Device
Application:
18/389,332 →
Publication:
US 2025/0157539
Apparatus and Methods for Managing Selector Device Threshold Voltage Drift
Application:
18/389,960 →
Publication:
US 2025/0210085
Apparatus and Methods for Managing Selector Device Threshold Voltage Drift
Application:
18/389,980 →
Publication:
US 2025/0210083
Bitscan Techniques in a Memory Device
Application:
18/389,982 →
Publication:
US 2025/0210117
Apparatus and Methods for Managing Selector Device Threshold Voltage Drift
Application:
18/389,987 →
Publication:
US 2025/0210084
Enhanced Bit Error Rate Estimation Scan Process
Dynamic Flash Interface Module (Fim) Optimization
Dynamic Bit Line Voltage During Program Verify to Provide More Threshold Voltage Budget
High Speed Receiver Circuitry
Application:
18/390,996 →
Publication:
US 2025/0211184
Word Line Switch Gate Voltage and Well Voltage Separation
Application:
18/391,560 →
Publication:
US 2025/0210108
Adaptable Electrostatic Discharge Clamp Trigger Circuit
Application:
18/391,792 →
Publication:
US 2025/0212527
Open Block Detection Using Current Consumption Peak During Fourth Time Period of Read Operation and Method of Lowering Current Consumption for Non-Volatile Memory Apparatus
Smart Reduced-Verify Algorithm for Non-Volatile Memory Apparatuses
Application:
18/392,904 →
Publication:
US 2025/0210105
Current Monitoring in a Memory Device to Improve Short Detection
Non-Volatile Memory with Leak Tests
Application:
18/393,557 →
Publication:
US 2025/0210124
Three-Dimensional Memory Device Containing Peripheral Circuit with Fin Field Effect Transistors and Method of Making the Same
Application:
18/396,150 →
Publication:
US 2024/0373639
Data Storage Device with Efficient Decoder Pool and Method for On-the-Fly Decoder Initialization
Non-Volatile Memory with Enhanced Early Program Termination Mode for Neighbor Plane Disturb
Just-In-Time Low Capacity DRAM Memory Allocation
Hybrid Memory Management of Non-Volatile Memory (Nvm) Devices for Use with Recurrent Neural Networks
Compact Sense Amplifier Data Latch Design with Very Low Voltage Transistors
Application:
18/409,292 →
Publication:
US 2025/0226038
Using Special Data Storage Parameters When Storing Cold Stream Data in a Data Storage Device
High Density Connector with Moveable Contacts
Application:
18/410,569 →
Publication:
US 2025/0233337
Wire Bonding Machine Having a Rotatable Capillary to Secure a Bond Wire to a Connection Point
Application:
18/410,668 →
Publication:
US 2025/0233102
Data Storage Device and Method for Read Disturb Mitigation During Low-Power Modes
Tolerating Defective Memory Banks in Emerging Memory Components
Application:
18/413,391 →
Publication:
US 2025/0231837
Power Efficient Unmatched Data Path Architecture for Non-Volatile Memory
Application:
18/414,004 →
Publication:
US 2025/0046351
Uniform Gidl Current During Nand Erase
Application:
18/415,224 →
Publication:
US 2025/0232817
Nonvolatile Memory with Temperature-Dependent Sense Time Offsets for Soft-Bit Read
Data Storage Device and Method for Configuring a Memory to Write a Requested Amount of Data Over the Memory's Lifetime
Application:
18/416,329 →
Publication:
US 2025/0238361
Three Dimensional Nand Multiply and Accumulate with Dynamic Inputs
Application:
18/417,239 →
Publication:
US 2025/0238202
Multiple Function Nonvolatile Memory Express (NVMe) Device (MFND) Performance Improvement By Over Reading
Application:
18/419,013 →
Publication:
US 2025/0238134
Non-Volatile Memory with in-Place Error Updating and Correction
Cavity Tape for Package Protection
Application:
18/419,588 →
Publication:
US 2025/0239497
Data Storage Device and Method for Host-Based Dynamic Jump Range Identification
Patent:
12,306,747 →
Application:
18/419,823 →
Pausing Garbage Collection During a Sequential Unmapping Process
Optimizing Usage Of Multiple Write Paths On Multi-Tenant Storage Devices
Three-Dimensional Memory Device Containing Split Support Pillar Structures and Methods of Making the Same
Application:
18/421,417 →
Publication:
US 2025/0113484
Dynamic Sensing Scheme to Compensate for Threshold Voltage Shift During Sensing in a Memory Device
Non-Target on-Die Termination
Feed-Forward Data Toggling Based Delay Circuit
Achieving Uniform Bandwidth Using Blended Memory Blocks for Relocation Operations
Application:
18/426,768 →
Publication:
US 2025/0244896
Two-Way Receptacle for Universal Serial Bus
Application:
18/426,878 →
Publication:
US 2025/0246837
Data Storage Device and Method for Accident-Mode Storage of Vehicle Information
Patent:
12,242,737 →
Application:
18/434,976 →
Using a Zone Wordline Table to Initiate a Find Last Good Page Process
Printed Circuit Board Having Lead Pads That Accommodate Offset Electronic Component Leads
Data Storage Device and Method for Hiding Tweak Generation Latency
Reference File Management for Artificial Intelligence Models
Data Storage Device and Method for Managing Memory Maintenance Operations
Patent:
12,307,100 →
Application:
18/441,095 →
Efficient Sequential Write Gap Processing
Application:
18/441,343 →
Publication:
US 2025/0258625
Data Storage Device and Method for Using an Adaptive, Configurable Storage Indirection Unit
Application:
18/442,624 →
Publication:
US 2025/0265185
Host Independent Formatting of Storage Devices
Raiseable Profile-Based Access for Media Content
Application:
18/446,442 →
Publication:
US 2024/0193241
Access Control System and a Data Storage Device
Application:
18/447,723 →
Publication:
US 2024/0362370
Dynamic Mode Selection for Hybrid Single-Level Cell and Multi-Level Cell Data Storage Devices
Method and Device for Secure Data Transfer and Storage
Storage of Control Data Information
Method and Device for Facilitating Secure Data Transfer and Storage
Write Aggregation Based on Nand Wear Level
Address Translation Service for Host Queues
Storage-Free Message Authenticators for Error-Correcting-Codes
Patent:
12,137,164 →
Application:
18/447,868 →
Devices, Methods, And Computer Readable Media For Control Page Flush Handling
Devices, Methods, and Computer-Readable Media to Back-up Parity Information
Devices, Methods, and Computer-Readable Media to Store Backed-up Parity Information
Dynamic Garbage Collection Operations
Application:
18/448,261 →
Publication:
US 2024/0264936
Capacitor Health Check For Data Storage Devices
Packaged Memory Device with Overhang Support Structure
Application:
18/448,296 →
Publication:
US 2024/0397735
Temperature Based Block Read
Application:
18/448,393 →
Publication:
US 2024/0249755
Stream Temperature Interleave Monitor
Application:
18/448,406 →
Publication:
US 2024/0232032
Server Thermal Management
Application:
18/448,633 →
Publication:
US 2024/0324147
Thermal Management in Data Storage Device
Selectable Performance Boost for Storage Devices
Selectable Performance-Based Partitioning
Computational SSD Supporting Rapid File Semantic Search
Application:
18/449,116 →
Publication:
US 2024/0119055
Error Correction Methods for Computational SSD Supporting Rapid File Semantic Search
Exposed Metal Loop to Detect Corrosion in a Data Storage Device
Segregating Large Data Blocks for Data Storage System
Semiconductor Chip with Varying Thickness Profile
Application:
18/449,452 →
Publication:
US 2024/0249950
Heat Harvesting in Data Storage Devices
Application:
18/449,483 →
Publication:
US 2024/0422938
Early Detection of Room Temperature Data Retention Phenomena
Selective Wire Coating During Wire Bonding
Application:
18/449,502 →
Publication:
US 2024/0429196
Access Control for Cloud-Shared Files from a Storage Device
Three-Dimensional Memory Devices Including Self-Aligned Channel Cap Structures and Methods for Forming the Same
Application:
18/450,095 →
Publication:
US 2024/0407164
Three-Dimensional Memory Device Including Inclined Word Line Contact Strips and Methods of Forming the Same
Application:
18/450,115 →
Publication:
US 2024/0414916
Three-Dimensional Memory Device Including Trench Bridge Structures Having Different Volumes and Methods of Forming the Same
Application:
18/450,150 →
Publication:
US 2024/0386959
Photolithography Method Using Castellation Shaped Assist Features to Form a Line-and-Space Pattern and Photomask Containing the Assist Features
Application:
18/451,206 →
Publication:
US 2025/0060672
Apparatus and Methods for Erasing for Non-Volatile Memory
Application:
18/452,500 →
Publication:
US 2025/0061947
Three-Dimensional Memory Device with Source Contact Layer Having Horizontally and Vertically Extending Portions and Methods of Forming the Same
Application:
18/452,737 →
Publication:
US 2025/0071998
Bonded Memory Mram Arrays Sharing a Common Driver Circuit and Methods of Making the Same
Non-Volatile Memory Bitmap for Garbage Collection
Phy Lanes Disabling for Power Efficiency
Three-Dimensional Memory Device with Through-Stack Contact via Structures and Method of Making the Same
Application:
18/455,988 →
Publication:
US 2024/0373633
Dynamically Determining a Ratio of Memory Blocks to Include in a Garbage Collection Process
Application:
18/456,856 →
Publication:
US 2025/0077102
Unsingulated Semiconductor Package
Application:
18/456,906 →
Publication:
US 2025/0079400
Stairless Three-Dimensional Memory Device with Layer Contact via Structures Located Above Support Pillar Structures and Methods of Forming the Same
Application:
18/457,883 →
Publication:
US 2025/0079294
Training Ensemble Models to Improve Performance in the Presence of Unreliable Base Classifiers
Application:
18/459,320 →
Publication:
US 2023/0419190
Three-Dimensional Memory Device with Pillar Shaped Trench Bridge Structures and Methods of Forming the Same
Application:
18/459,938 →
Publication:
US 2025/0081458
Credit Allocation for Enabling Access to Hardware Resources of a Computing Device
Application:
18/461,089 →
Publication:
US 2025/0077258
Memory Testing Flow Set Up with Computational Intelligence
HMB Random and Sequential Access Coherency Approach
Application:
18/461,777 →
Publication:
US 2025/0077453
FAIRNESS AND CONSISTENCY IN MULTI-FUNCTION NONVOLATILE MEMORY (NVM) EXPRESS (NVMe) DEVICE (MFND)
Resource Allocation to Avoid Command Timeouts in a Storage Device
Application:
18/461,939 →
Publication:
US 2025/0077287
Chemical Mechanical Polishing Process Using Steam for Polishing Fluid Delivery and an Apparatus for Implementing the Same
Application:
18/462,830 →
Publication:
US 2025/0083282
Memory Device Including Word Line Contact Strips and Methods of Forming the Same
Application:
18/462,955 →
Publication:
US 2024/0414917
Location-Based Maintenance Operations for a Data Storage Device
Block Data Encryption of Non-Volatile Memory Through Selective Select Gate Erase Through Charge Coupled Scheme
Memory Die Stack Having a Switch for Selectively Connecting a Memory Die to a Substrate
Application:
18/463,805 →
Publication:
US 2025/0089271
Cache Writing to Zones to Maximize Write Bandwidth
Patent:
12,223,175 →
Application:
18/464,503 →
Back Grinding Tape Having Tabs to Assist in Removing the Back Grinding Tape from a Wafer
Application:
18/464,779 →
Publication:
US 2025/0087519
Apparatus and Methods for Back-to-Back State Machine Controller Bus Operations
Semiconductor Device Fabrication Method Using a Deposition Apparatus with a Contoured Wafer Carrier Ring
Application:
18/466,108 →
Publication:
US 2025/0087525
Data Path Oscillator Mismatch Error Reduction for Non-Volatile Memory
Non-Volatile Memory with Efficient Precharge in Sub-Block Mode
Stair-Step Configuration for a Semiconductor Die of an Integrated Circuit
Application:
18/468,904 →
Publication:
US 2025/0096058
Non-Volatile Memory with Sequential Read
Application:
18/471,455 →
Publication:
US 2025/0104777
Three-Dimensional Memory Device with Isolation Trench Fill Structure Having Laterally-Undulating Sidewalls and Method of Making the Same
Application:
18/471,896 →
Publication:
US 2025/0107079
Managing Streams Based on Predicted Host Commands
Scheduling Execution of Commands in a Data Storage Device Based on Command Parameters
Application:
18/473,774 →
Publication:
US 2025/0103381
Trench Patterning Process Using Microcracking
Application:
18/475,826 →
Publication:
US 2025/0107083
Three-Dimensional Memory Device Containing Laterally Undulating Isolation Trenches and Methods of Making the Same
Application:
18/477,907 →
Publication:
US 2025/0113485
Capillary for a Wire Bonding Machine Having a Dynamically Adjustable Chamfer Diameter
Application:
18/478,358 →
Publication:
US 2025/0149502
Three-Dimensional Memory Device Containing Phosphorus-Doped Silicon Oxide Ion-Gettering Structures and Methods of Forming the Same
Application:
18/479,432 →
Publication:
US 2025/0113486
Key-Group Based Data Management in Kv Ssd
Application:
18/480,671 →
Publication:
US 2025/0117152
Non-Volatile Memory with Current Detection Circuit
Read for Memory Cell with Threshold Switching Selector
Artificial Select Gate Cut for Nand
Read in Multi-Tier Non-Volatile Memory
Application:
18/483,010 →
Publication:
US 2025/0118376
Adaptive Tuning Of Memory Device Clock Rates Based On Usage Workloads
Erase Type Detection Mechanism
Smart Host Stream Release
Application:
18/485,070 →
Publication:
US 2025/0123760
Data Transfer for Vehicles
Three-Dimensional Memory Device Including Sloping Word Lines for Stairless Contact and Methods of Forming the Same
Application:
18/488,360 →
Publication:
US 2025/0126784
Improved Host Dram and Pcie Bandwidth Utilization for Dram-Less Devices
Application:
18/488,421 →
Publication:
US 2025/0123747
Write Protect HW Acceleration
Bandwidth Averaging In A Stochastic System
SSD Optimization Awareness To Atomicity Of Different System Files
Read-Protected Storage Device With Sequential Logging
Read Recovery with Time Limit in Nonvolatile Memory
Metal Lines Located Between Etch Stop Layers and Separated by Air Gaps and Methods of Forming the Same
Application:
18/491,297 →
Publication:
US 2025/0132301
Suppression of Peak Icc During Block Selection in Non-Volatile Memories
Three-Dimensional Memory Device with Different Width Support Pillar Structures and Methods of Making the Same
Application:
18/493,036 →
Publication:
US 2025/0133737
Micro Solder Joint and Stencil Aperture Design
Application:
18/493,379 →
Publication:
US 2024/0057261
Semiconductor Wafer Thinned by Crack Propagation
Application:
18/493,527 →
Publication:
US 2025/0132205
Integrated Charge Pump Testing Circuits
Application:
18/494,852 →
Publication:
US 2025/0139344
Three-Dimensional Memory Device Containing Dummy via Cavities and Method for Making Same
Application:
18/495,534 →
Publication:
US 2025/0140688
Peripheral Circuit with Semiconductor Pillar Containing Local Interconnects and Methods for Forming the Same
Application:
18/495,552 →
Publication:
US 2025/0142913
Cross-Point Ovonic Memory Device Having Different Size Electrodes and Method of Making the Same
Application:
18/499,325 →
Publication:
US 2025/0040155
Sub-Block Separation in Nand Memory Through Word Line Based Selectors
Efficient Address Translation Cache Lookup Operations
Multi-Functional Universal Serial Bus (USB) Drive
Accessing Shared Partitions on a Storage Drive of a Remote Device
Application:
18/501,490 →
Publication:
US 2024/0064149
Eco-Friendly Printed Circuit Board for High Temperature and Low Temperature Applications
Speculative Address Translation Service Requests
Burst Awareness Scheduler Over Host Interface
Data Routing In Networked SSDs
Hybrid Address Translation Cache Using DRAM
Creating a Solder Barrier by Changing a Material Property of a Trace on a Printed Circuit Board
Application:
18/504,408 →
Publication:
US 2025/0151206
Determining a Back Drilling Depth for a Printed Circuit Board Using a Printed Circuit Board Test Coupon
Application:
18/504,413 →
Publication:
US 2025/0147097
Optimizations For Payload Fetching In NVMe Commands
Application:
18/505,292 →
Publication:
US 2025/0156313
Nonvolatile Memory with Distributed Xor Protection
Peer-To-Peer Communication Using Drain Buffers In Multi-Function Device
Application:
18/506,281 →
Publication:
US 2025/0156347
Non-Volatile Memory with Three Dimensional Stacked Word Line Switches
Patent:
11,943,922 →
Application:
18/507,026 →
Even/Odd Word Line Driving in 3D Memory
Application:
18/508,554 →
Publication:
US 2025/0157538
Three-Dimensional Memory Device Containing Laterally Undulating Isolation Trenches and Methods of Making the Same
Application:
18/508,638 →
Publication:
US 2025/0113492
Bonding Structures for High-Density Metal-to-Metal Bonding and Methods for Forming the Same
Application:
18/509,010 →
Publication:
US 2025/0157963
Bonding Structures for High-Density Metal-to-Metal Bonding and Methods for Forming the Same
Application:
18/509,035 →
Publication:
US 2025/0157964
Bonding Structures for High-Density Metal-to-Metal Bonding and Methods for Forming the Same
Application:
18/509,051 →
Publication:
US 2025/0157965
Erase Verify Mode to Reduce Power Consumption in Erase Operation of Non-Volatile Memory Apparatus
Application:
18/509,523 →
Publication:
US 2025/0157552
Variable Foggy Verify Levels for Selected Checkpoint States for Non-Volatile Memory Apparatuses
Delayed Select Gate Ramp-Up for Peak Read Current Consumption Reduction for Non-Volatile Memory Apparatus
Dynamic Program Performance Modulation in a Memory Device
Application:
18/510,070 →
Publication:
US 2025/0157541
Sense Time Separation in Foggy-Fine Program to Improve Optimal Vt Width
On-Chip Qlc and Tlc Mix Operation
Application:
18/511,333 →
Publication:
US 2025/0165181
Method for Detecting and Recovering an Inoperable Drive
Application:
18/511,724 →
Publication:
US 2025/0165345
Proactive Correction Of Potential Transmission Errors In A Storage Device
Application:
18/513,949 →
Publication:
US 2025/0165321
TLC Data Programming With Hybrid Parity
Cache Write Overlap Handling
Enhanced Prying Structure for an Electronic Device
Three-Dimensional Memory Device Including Crack-Resistant Backside Passivation Structure and Methods of Forming the Same
Three-Dimensional Memory Device Including Crack-Resistant Backside Passivation Structure and Methods of Forming the Same
Application:
18/516,170 →
Publication:
US 2025/0169070
DRAM-Less SSD With Command Draining
Time Tag Word Line Shift to Reduce Failed Bit Count Spikes for Edge Word Lines
Processing Core Including Integrated High Capacity High Bandwidth Storage Memory
Smart Erase Inhibit
Non-Volatile Memory with Operation Adjustment Based on Open Block Ratio and Cycling
Application:
18/519,962 →
Publication:
US 2025/0173088
Sot Mram Including Mtj and Selector Located on Opposite Sides of Sot Layer and Method of Making the Same
Application:
18/520,299 →
Publication:
US 2025/0176192
Sot Mram Including Mtj and Selector Located on Opposite Sides of Sot Layer and Method of Making the Same
NVMe Completion And Interrupt
Application:
18/522,514 →
Publication:
US 2025/0173283
Three-Dimensional Memory Device with Variable Word Line via Contact Density as Function of Contact Depth and Methods of Forming the Same
Application:
18/523,129 →
Publication:
US 2025/0174550
Memory Die with on-Chip Binary Vector Database Search
Memory Die with on-Chip Binary Vector Database Search
Deterministic Bandwidth for a Data Storage Device
Application:
18/528,736 →
Publication:
US 2025/0181256
Bonding Structures for High-Density Metal-to-Metal Bonding and Methods for Forming the Same
Application:
18/530,953 →
Publication:
US 2025/0157966
Three-Dimensional Memory Device with Through-Stack Contact via Structures and Method of Making the Same
Application:
18/532,221 →
Publication:
US 2024/0215243
Apparatus and Methods for Read Retry with Conditional Data Refresh
Quality of Service (Qos) Optimized Open Block Closure
Optimized Handling of High Current Consumption During an Open Block Read
Method for Optimizing Interface Training on a Storage Device
Minimizing Redundancy for Stuck Bit Coding
Efficient Assembly for Electrolytic Capacitors on Solid State Drives
Application:
18/534,409 →
Publication:
US 2025/0194016
Management and Storage of Neural Network Weights
Application:
18/538,890 →
Publication:
US 2025/0200390
Flexible Sized Super Block for Optimized Performance and Endurance
Application:
18/541,811 →
Publication:
US 2025/0199702
Logical Block Formation Based on Block Erase Loops
Application:
18/541,892 →
Publication:
US 2025/0199707
SSD Auxiliary Battery Power For Handling Ungraceful Shutdown With Host
Removable Memory Card with Efficient Card Lock Mechanism, XY Ratios, Anti-Reverse Insertion Feature, Pullout Feature, and Pads Layout
Application:
18/545,527 →
Publication:
US 2025/0139395
Hybrid Thermal Interface Material with Embedded Metal Layer
Application:
18/545,601 →
Publication:
US 2025/0201657
Multi-Stage Decoder with Adaptive Learning
Optimized Handling of Neighbor Plane Disturb Issues
Allocating Data Storage Device Resources Based on Determined Capabilities of a Host Device
Application:
18/583,061 →
Publication:
US 2025/0265186
Storage Device Cooling Air Ventilation Features
Application:
18/583,458 →
Publication:
US 2025/0267817
Handling Grown Bad Blocks in a Memory Device
Step-Down Printed Circuit Board with a Flexible Connector
Application:
18/584,729 →
Publication:
US 2025/0275057
Adding Sacrificial Traces to Aborb Signal Interference from High Speed Aggressor Traces
Application:
18/585,866 →
Publication:
US 2025/0273591
Data Storage Device and Method for Managing a Hot Count Difference in Sub-Block Mode
Apparatus and Methods for Reducing Number of Layout Tracks for Sense Amplifiers
Application:
18/587,700 →
Publication:
US 2025/0275146
Deterministic Resizing of Unmap Commands
Patent:
12,307,133 →
Application:
18/589,138 →
Data Storage Device and Method of Access in Confidential Mode and Normal Mode
Data Storage Device and Method for Data Routing for Wear Levelling in Multi-Meta-Die Data Storage Devices
Multi-Protocol Data Storage Device and Method for Sustained Write Performance
Low Error Rate Read Operation in Multi-Module Arrays
Application:
18/591,904 →
Publication:
US 2025/0279127
Self-Learning Built-in Self-Test (Bist) for Leak Detection in Non-Volatile Memory
Read Parameter Zoning
Data Storage Device and Method for Multi-Tenant Dynamic Bandwidth Reallocation
Application:
18/603,525 →
Publication:
US 2025/0291645
Semiconductor Package Having an Integrated Passive Device That Acts as a Spacer
Application:
18/606,010 →
Publication:
US 2025/0293218
Storing Multiple Versions of Preloaded Content to Mitigate Cross-Temperature Impact
Application:
18/608,265 →
Publication:
US 2025/0291480
Predictive Adjustment of Distributed Surveillance Video Data Capture Using Networks of Graph Maps
Processing Core Including Integrated High Capacity High Bandwidth Storage Memory
Application:
18/608,695 →
Publication:
US 2025/0293205
Solution for Super Device Imbalance in ZNS SSD
Application:
18/609,042 →
Publication:
US 2024/0220155
Data Storage Device and Method for Dynamic Flash Interface Module (FIM) Load Balancing for Memory Die Sharing
Application:
18/610,423 →
Publication:
US 2025/0298663
Method of Making High Aspect Ratio Openings in a Semiconductor Device Using Ion Implantated Regrown Cladding Mask
Nonvolatile Memory with Fast Program Voltage Ramp Down
Application:
18/614,774 →
Publication:
US 2025/0299739
Storage Methods and Devices with Secure Customer-Updatable Machine Learning Models
Application:
18/615,678 →
Publication:
US 2025/0298880
Built-In Self-Test Circuitry for Data in Path for Non-Volatile Memory with Multiple Test Clock Speeds for Multiple Test Modes
Embedded Aligned Fiducial Markers for Stacked Fanout Semiconductor Device
Application:
18/621,497 →
Publication:
US 2025/0309196
Column Redundancy Data Circuits and Methods for Higher Transmit Speed
Combined External Storage Device and Removable Portable Memory Key
Patent:
639,297 →
Application:
29/370,333 →
Nesting and Shock Absorbing Package
Patent:
833,301 →
Application:
29/592,244 →
Electronic Device for Charging, Data Storage, or Data Transfer
Patent:
917,472 →
Application:
29/690,857 →
Portable Data Storage Device
Patent:
917,473 →
Application:
29/695,667 →
Data storage Device
Patent:
1,019,668 →
Application:
29/775,446 →
Data Storage Device
Patent:
1,019,637 →
Application:
29/775,449 →
Data Storage Device Holder
Patent:
1,062,755 →
Application:
29/853,777 →
Data Storage Device
Patent:
1,096,734 →
Application:
29/928,447 →
Data Storage Device
Patent:
1,090,554 →
Application:
29/928,458 →
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jun 21, 2002
From: HOSPODOR, ANDREW D.
To: PLUSTREAM, INC.
Reel/Frame 013034/0666 →
Confirmation of Assignment
Aug 31, 2005
From: COROSOFT, INC. (FORMERLY KNOWN AS PLUSTREAM, INC.)
To: WESTERN DIGITAL VENTURES, INC.
Reel/Frame 016704/0310 →
Change of Name
Oct 25, 2012
From: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
To: HGST NETHERLANDS B.V.
Reel/Frame 029341/0777 →
Assignment of Assignor's Interest
Oct 23, 2015
From: SILICONSYSTEMS, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 036872/0017 →
Security Agreement
May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
Security Agreement
May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
Security Agreement
May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
Assignment of Assignor's Interest
Dec 5, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040820/0802 →
Assignment of Assignor's Interest
Dec 5, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040819/0450 →
Assignment of Assignor's Interest
Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040821/0550 →
Release of Security Interest
Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
Assignment of Assignor's Interest
May 16, 2018
From: HGST TECHNOLOGIES SANTA ANA, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046174/0446 →
Assignment of Assignor's Interest
Aug 24, 2018
From: HGST, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046939/0587 →
Security Interest
Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
Assignment of Assignor's Interest
May 28, 2020
From: HGST NETHERLANDS B.V
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052783/0631 →
Security Interest
Jun 9, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052888/0177 →
Change of Name
Jun 11, 2020
From: WESTERN DIGITAL VENTURES, INC
To: WESTERN DIGITAL CAPITAL, INC
Reel/Frame 052919/0177 →
Change of Name
Jun 15, 2020
From: WESTERN DIGITAL CAPITAL, INC
To: WESTERN DIGITAL CAPITAL, LLC
Reel/Frame 052945/0476 →
Assignment of Assignor's Interest
Jul 14, 2020
From: WESTERN DIGITAL CAPITAL, LLC
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053208/0828 →
Security Interest
Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
Release of Security Interest at Reel 052915 Frame 0566
Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
Release of Security Interest at Reel 038744 Frame 0481
Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
Release of Security Interest at Reel 053926 Frame 0446
Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
Release of Security Interest at Reel 052888 Frame 0177
Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0712 →
Release of Security Interest at Reel 039389 Frame 0684
Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0535 →