IP Library Granted Patent US 11,175,983
Granted Patent B2
US 11,175,983 · App. 16/823,235 · Granted Nov 16, 2021

Soft-decision input generation for data storage systems

Inventors: Guangming Lu (Irvine, CA); Kent D. Anderson (Broomfield, CO); Anantha Raman Krishnan (Irvine, CA); Shafa Dahandeh (Laguna Niguel, CA)
Assignee: Western Digital Technologies, Inc.
G06F11/1012G06F11/10
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Quick Facts
Patent No.
US 11,175,983
App. No.
16/823,235
Granted
Nov 16, 2021
Kind
B2
Abstract

An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

Claims (60)

1. A computer-implemented method, comprising:

obtaining a first data stored in a first memory location of a memory;

generating read values, based on a plurality of reads performed on the first data;

computing a plurality of log likelihood ratios (LLRs), based on the read values and the first data; and

when one or more second memory locations of the memory are physically located within a target value,

selecting one or more LLRs from the plurality of LLRs; and

decoding data stored in the one or more second memory locations using the selected one or more LLRs.

2. The computer-implemented method of claim 1 , wherein

the target value is a target proximity value,

wherein the computer-implemented method comprises: obtaining one or more first data retention characteristics of the first memory location and one or more second data retention characteristics of the one or more second memory locations, and

wherein selecting the one or more LLRs comprises selecting the one or more LLRs based on the one or more first data retention characteristics and the one or more second data retention characteristics.

3. The computer-implemented method of claim 1 , wherein

the read values are correlated with the first data.

4. The computer-implemented method of claim 1 , comprising: placing the plurality of LLRs into a data structure associated with the first memory location.

5. The computer-implemented method of claim 4 , comprising: periodically updating one or more LLRs of the plurality of LLRs in the data structure, based on one or more decode operations performed on the data stored in the one or more second memory locations.

6. The computer-implemented method of claim 1 , comprising:

determining whether data in a third memory location is successfully decoded using a first read voltage; and

when the third memory location is not successfully decoded using the first read voltage:

decoding data in a fourth memory location using the first read voltage; and

when the data in the fourth memory location is successfully decoded using the first read voltage:

treating the data in the fourth memory location as the first data.

7. The computer-implemented method of claim 6 , comprising: when the third memory location is successfully decoded using the first read voltage, treating the data in the third memory location as the first data.

8. A data storage system, comprising:

a memory; and

a controller configured to cause:

obtaining a first data stored in a first memory location of the memory;

generating read values, based on a plurality of reads performed on the first data;

computing a plurality of log likelihood ratios (LLRs), based on the read values and the first data; and

when one or more second memory locations of the memory are physically located within a target value,

selecting one or more LLRs from the plurality of LLRs; and

decoding data stored in the one or more second memory locations using the selected one or more LLRs.

9. The data storage system of claim 8 , wherein the controller is configured to cause: obtaining one or more first data retention characteristics of the first memory location and one or more second data retention characteristics of the one or more second memory locations,

wherein selecting the one or more LLRs comprises selecting the one or more LLRs based on the one or more first data retention characteristics and the one or more second data retention characteristics.

10. The data storage system of claim 8 , wherein the read values are correlated with the first data.

11. The data storage system of claim 8 , wherein the controller is configured to cause: placing the plurality of LLRs into a data structure associated with the first memory location.

12. The data storage system of claim 11 , wherein the controller is configured to cause: periodically updating one or more LLRs of the plurality of LLRs in the data structure, based on one or more decode operations performed on the data stored in the one or more second memory locations.

13. The data storage system of claim 8 , wherein the controller is configured to cause:

determining whether data in a third memory location is successfully decoded using a first read voltage; and

when the third memory location is not successfully decoded using the first read voltage:

decoding data in a fourth memory location using the first read voltage; and

when the data in the fourth memory location is successfully decoded using the first read voltage:

identifying the data in the fourth memory location as the first data.

14. The data storage system of claim 13 , wherein the controller is configured to cause: when the third memory location is successfully decoded using the first read voltage, identifying the data in the third memory location as the first data.

15. An apparatus, comprising:

means for obtaining a first data stored in a first memory location of a memory;

means for generating read values, based on a plurality of reads performed on the first data;

means for computing a plurality of log likelihood ratios (LLRs), based on the read values and the first data; and

when one or more second memory locations of the memory are physically located within a target value,

means for selecting one or more LLRs from the plurality of LLRs; and

means for decoding data stored in the one or more second memory locations using the selected one or more LLRs.

16. The apparatus of claim 15 , comprising: means for obtaining one or more first data retention characteristics of the first memory location and one or more second data retention characteristics of the one or more second memory locations,

wherein means for selecting the one or more LLRs comprises means for selecting the one or more LLRs based on the one or more first data retention characteristics and the one or more second data retention characteristics.

17. The apparatus of claim 15 , wherein the read values are correlated with the first data.

18. The apparatus of claim 15 , comprising: means for placing the plurality of LLRs into a data structure associated with the first memory location.

19. The apparatus of claim 18 , comprising: means for periodically updating one or more LLRs of the plurality of LLRs in the data structure, based on one or more decode operations performed on the data stored in the one or more second memory locations.

20. The apparatus of claim 15 , comprising:

when data in a third memory location is not successfully decoded using a first read voltage:

means for decoding data in a fourth memory location using the first read voltage; and

when the data in the fourth memory location is successfully decoded using the first read voltage, means for treating the data in the fourth memory location as the first data; and

when the data in the third memory location is successfully decoded using the first read voltage, means for treating the data in the third memory location as the first data.

Assignments (10)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2020
From: LU, GUANGMING; ANDERSON, KENT D.; KRISHNAN, ANANTHA RAMAN; DAHANDEH, SHAFA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052338/0345 →
Continuity (3)
Continuation 16112429 · Aug 24, 2018
Continuation 13797943 · Mar 12, 2013
Related Publication 20200218596A1 · Jul 9, 2020