IP Library Granted Patent US 9,830,257
Granted Patent B1
US 9,830,257 · App. 13/967,292 · Granted Nov 28, 2017

Fast saving of data during power interruption in data storage systems

Inventors: Jing Booth (San Jose, CA); Stephen J. Silva (Fort Collins, CO); Justin Ha (San Francisco, CA)
Assignee: Western Digital Technologies, Inc.
G06F12/0246G11C14/0018G11C14/0063
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Quick Facts
Patent No.
US 9,830,257
App. No.
13/967,292
Granted
Nov 28, 2017
Kind
B1
Abstract

Embodiments of systems and methods that ensure integrity of data during unexpected power interruption of loss are disclosed. In some embodiments, critical data is saved quickly and efficiently using backup power. Data integrity is ensured even when the reliability of backup power sources is an issue. In some embodiments, by skipping the updating and saving of system data while operating on backup power, significant reduction of time for saving critical data can be achieved. System data can be restored next time the data storage system is restarted. Improvements of data storage system reliability are thereby attained.

Claims (36)

1. A non-volatile data storage system, comprising:

a non-volatile memory array comprising a plurality of memory die;

a volatile memory; and

a controller configured to:

maintain a mapping associating a set of physical addresses in the non-volatile memory array where host system data is stored with a set of logical addresses, wherein at least a portion of the mapping is stored in the volatile memory during operation,

detect, on an indication of a power shutdown, whether the power shutdown is an unexpected interruption of power or an expected interruption of power,

in response to detecting the unexpected interruption of power, write host system data stored in the volatile memory along with one or more mapping data headers to one or more first memory locations in one or more super blocks of the non-volatile memory array, each superblock comprising a plurality of memory blocks in multiple memory die of the plurality of memory die, the one or more mapping data headers comprising physical addresses of second memory locations within the non-volatile memory array that are designated for storing the host system data written to the one or more first memory locations in response to detecting the unexpected interruption of power, the first memory locations being different than the second memory locations, the host system data and one or more mapping data headers being written without updating the mapping or storing mapping updates in the non-volatile memory array, and

upon resuming operation following the unexpected interruption of power, scan the one or more superblocks for the one or more mapping data headers comprising the physical addresses of the second memory locations.

2. The non-volatile data storage system of claim 1 , wherein the one or more mapping data headers comprises one or more logical addresses associated with host system data stored in the volatile memory and written to the non-volatile memory array.

3. The non-volatile data storage system of claim 2 , wherein, upon resuming operation following the unexpected interruption of power, the controller is further configured to update the mapping using the one or more mapping data headers.

4. The non-volatile data storage system of claim 1 , wherein the controller is further configured to:

in response to detecting the unexpected interruption of power, store in a boot memory region of the non-volatile memory array identification information corresponding to one or more non-volatile memory array regions where host system data stored in the volatile memory is written.

5. The non-volatile data storage system of claim 4 , wherein, upon resuming operation following the unexpected interruption of power, the controller is further configured to update the mapping using the one or more mapping data headers metadata.

6. The non-volatile data storage system of claim 5 , further comprising a hardware module configured to scan the one or more non-volatile memory array regions where host system data stored in the volatile memory was written for the one or more mapping data headers.

7. The non-volatile data storage system of claim 1 , further comprising a primary power source configured to provide power during operation and a backup power source configured to provide power during the unexpected interruption of power provided by the primary power source.

8. The non-volatile data storage system of claim 7 , wherein the backup power source comprises one or more of capacitors or other power storage devices.

9. The non-volatile data storage system of claim 1 , wherein the controller is further configured to:

in response to detecting the expected interruption of power, perform shutdown operations comprising writing host system data stored in the volatile memory to the non-volatile memory array, updating the mapping, and storing mapping updates in the non-volatile memory array.

10. The non-volatile data storage system of claim 1 , wherein the controller is further configured to power off the volatile memory after host system data stored in the volatile memory has been stored in the non-volatile memory array.

11. In a non-volatile data storage system comprising a controller, a volatile memory, and a non-volatile memory array comprising a plurality of memory die, a method of storing data, the method comprising:

maintaining a mapping associating a set of physical addresses in the non-volatile memory array where host system data is stored with a set of logical addresses, wherein at least a portion of the mapping is stored in the volatile memory during operation;

detect, on an indication of a power shutdown, whether the power shutdown is an unexpected interruption of power or an expected interruption of power;

in response to detecting an unexpected interruption of power, writing host system data stored in the volatile memory along with one or more mapping data headers to one or more first memory locations in one or more super blocks of the non-volatile memory array, each superblock comprising a plurality of memory blocks in multiple memory die of the plurality of memory die, the one or more mapping data headers comprising physical addresses of second memory locations within the non-volatile memory array that are designated for storing the host system data written to the one or more first memory locations in response to detecting the unexpected interruption of power, the first memory locations being different than the second memory locations, the host system data and one or more mapping data headers being written without updating the mapping or storing mapping updates in the non-volatile memory array; and

upon resuming operation following the unexpected interruption of power, scanning the one or more superblocks for the one or more mapping data headers comprising the physical addresses of the second memory locations,

wherein the method is performed under control of the controller.

12. The method of claim 11 , wherein the one or more mapping data headers comprises one or more logical addresses associated with host system data stored in the volatile memory and written to the non-volatile memory array.

13. The method of claim 12 , further comprising updating the mapping using the one or more mapping data headers upon resuming operation following the unexpected interruption of power.

14. The method of claim 11 , further comprising:

in response to detecting the unexpected interruption of power, storing in a boot memory region of the non-volatile memory array identification information corresponding to one or more non-volatile memory array regions where host system data stored in the volatile memory is written.

15. The method of claim 14 , further comprising:

upon resuming operation following the unexpected interruption of power updating the mapping using the one or more mapping data headers.

16. The method of claim 11 , further comprising providing power during operation from a primary power source and providing power during the unexpected interruption of power provided by the primary power source from a backup power source.

17. The method of claim 16 , wherein the backup power source comprises one or more of capacitors or other power storage devices.

18. The method of claim 11 , further comprising:

in response to detecting the expected interruption of power, performing shutdown operations comprising writing host system data stored in the volatile memory to the non-volatile memory array, updating the mapping, and storing mapping updates in the non-volatile memory array.

19. The method of claim 11 , further comprising powering off the volatile memory after host system data stored in the volatile memory has been stored in the non-volatile memory array.

Assignments (13)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2013
From: BOOTH, JING; SILVA, STEPHEN J.; HA, JUSTIN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 031012/0080 →
Continuity (1)
Provisional Application 61834229 · Jun 12, 2013