Granted Patent B2

US 8,762,798 · App. 13/678,416 · Granted Jun 24, 2014

Abstract

Claims (52)

1. A method for adjusting a code rate in a solid-state drive, the method comprising:

storing host data in a first plurality of memory units of a flash memory device using a first code rate;

monitoring an operating condition associated with the flash memory device for a trigger event;

adjusting, on the trigger event, the first code rate in accordance with the operating condition to produce a second code rate; and

storing host data in a second plurality of memory units of the flash memory device using the second code rate.

2. The method of claim 1 , wherein the operating condition comprises a number of program/erase (P/E) cycles.

3. The method of claim 2 , wherein the trigger event comprises the number of P/E cycles satisfying a threshold number of P/E cycles.

4. The method of claim 2 , further comprising:

determining, on the trigger event, the second code rate by indexing a lookup table by a current range of P/E cycles.

5. The method of claim 1 , wherein the operating condition comprises an error rate.

6. The method of claim 5 , wherein the trigger event comprises the error rate satisfying a threshold error rate.

7. The method of claim 5 , further comprising:

determining, on the trigger event, the second code rate by indexing a lookup table by a current range of error rates.

8. The method of claim 1 , further comprising:

decoding host data from the first plurality of memory units at the first code rate; and

decoding host data from the second plurality of memory units at the second code rate.

9. The method of claim 1 , further comprising:

storing a code rate flag in connection with encoding host data for one or more respective memory units;

determining, in connection with reading one or more respective memory units, a decoding code rate based on the stored code rate flag for one or more respective memory units; and

decoding host data for one or more respective memory units based on the determined decoding code rate.

10. The method of claim 1 , wherein adjusting the first code rate comprises:

reducing the first code rate by an amount predetermined to sustain a raw read error rate associated with one or more memory blocks below a predetermined threshold for a predetermined number of P/E cycles.

11. The method of claim 1 , wherein the second code rate has a lower code rate value than the first code rate.

12. The method of claim 1 , wherein adjusting the first code rate modifies an amount of storage available for user data in future operations.

13. The method of claim 1 , wherein the code rate is a LDPC code rate.

14. A non-transitory machine-readable medium having instructions stored thereon that, when executed, cause a machine to perform a method for adjusting a code rate in a solid state drive, the method comprising:

receiving a first quantity of host data;

encoding, for storage in a first plurality of memory units, a first quantity of host data at a first code rate, the first code rate corresponding to a predetermined code rate value;

storing the encoded first quantity of host data in the first plurality of memory units;

monitoring one or more operating conditions associated with the one or more memory units for a trigger event;

adjusting, on a predetermined trigger event, the code rate value;

receiving a second quantity of host data;

encoding, for storage in a second plurality of memory units, a second quantity of host data at a second code rate; and

storing the encoded second quantity of host data in the second plurality of memory units.

15. The non-transitory machine readable medium of claim 14 , wherein adjusting the code rate value comprises:

adjusting the code rate value by an amount sufficient to reduce, below a predetermined threshold, a read error rate produced in connection with future memory operations.

16. The non-transitory machine readable medium of claim 14 , wherein the one or more operating conditions comprise an error rate or a number of program/erase cycles, and wherein the trigger event comprises a threshold error rate or threshold program/erase cycle.

17. The non-transitory machine readable medium of claim 14 , further comprising:

decoding host data from the first plurality of memory units at the first code rate; and

decoding host data from the second plurality of memory units at the second code rate.

18. The non-transitory machine readable medium of claim 14 , further comprising:

storing a code rate flag in connection with encoding host data for the one or more memory units;

determining, in connection with reading one or more respective memory units, a decoding code rate based on the stored code rate flag for one or more respective memory units; and

decoding host data from one or more respective memory units based on the determined decoding code rate.

19. The non-transitory machine readable medium of claim 14 , wherein the code rate is a LDPC code rate.

20. A system, comprising:

a flash controller;

one or more flash memory devices; and

one or more embedded memories associated with the controller, the memories having instructions stored thereon that, when executed, cause the flash controller to:

monitor one or more operating conditions associated with the one or more flash memory devices for one or more trigger events; and

adjust, on a predetermined trigger event, a LDPC code rate used in current memory operations performed by the flash controller by an amount sufficient to reduce, below a predetermined threshold, a read error rate produced in connection with future memory operations,

wherein host data is stored in a first plurality of memory units using a first code rate before the LDPC code rate is adjusted, and host data is stored in a second plurality of memory units using a second code rate after the LDPC code rate is adjusted.

Assignments (12)