IP Library Granted Patent US 11,907,587
Granted Patent B2
US 11,907,587 · App. 17/343,357 · Granted Feb 20, 2024

Managing persistent memory regions across multiple protocols

Inventors: Pradeep Sreedhar (Bangalore, IN); Ramanathan Muthiah (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0661G06F3/061G06F3/0676G06F3/0677G06F3/0679G06F3/0682
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Quick Facts
Patent No.
US 11,907,587
App. No.
17/343,357
Granted
Feb 20, 2024
Kind
B2
Abstract

Storage devices are described herein that are capable of communicating with host-computing devices using multiple protocols. These Multi-Protocol Storage Devices (MPSDs) can be configured to utilize a persistent memory region (PMR) across a variety of protocols. Often, one of these protocols is the Non-Volatile Memory express (NVMe) protocol which provides for the ability to utilize and manage a PMR within the storage device. Other protocols may not have native support for PMR like the NVMe protocol does. Therefore, MPSDs are disclosed that may determine which protocol is in use in response to an initialization event and adjust the use of the PMR as needed based on the determined protocol. These adjustments may allow for the direct access of the PMR as an extension of general memory storage or may be configured to provide increased performance of the storage device overall. These storage devices may be hot-swappable between numerous host-computing systems.

Claims (58)

1. A method of managing a persistent memory region (PMR) within a device, comprising:

configuring operation under a plurality of protocols through a single interface, wherein at least one of the plurality of protocols is a Non-Volatile Memory Express (NVMe) protocol;

initializing the device;

determining a protocol for operation:

wherein if the determined protocol is an NVMe protocol:

a PMR usage threshold is determined;

data associated with the PMR is loaded; and

the device is operated under the determined NVMe protocol; and

wherein if the determined protocol is a second protocol, the device is operated under the determined second protocol;

physically decoupling the device from a first host-computing device;

physically coupling the device to a second host-computing device operating under a second protocol; and

determining the second protocol.

2. The method of claim 1 , wherein the device is configured as a Secure Digital Express (SDX) device.

3. The method of claim 1 , wherein the device is coupled to a first host-computing device operating under a first protocol.

4. The method of claim 1 , wherein the determination of the second protocol is triggered by an initialization event.

5. The method of claim 4 , wherein the initialization event occurs in response to the coupling of the device to the second host-computing device.

6. The method of claim 4 , wherein the first and second host-computing devices provide power to the device.

7. The method of claim 6 , wherein the initialization event occurs in response to a restoration of power upon coupling the device to the second host-computing device.

8. A device, comprising:

a processor;

a memory comprising a Persistent Memory Region (PMR) configured to operate under multiple protocols through a single interface wherein a first protocol is a Non-Volatile Memory Express (NVMe) protocol;

a Non-Volatile Memory (NVM) array organized into logical blocks; and

a persistent memory device (PMD) organized into logical blocks:

wherein PMR data is loaded into the PMD from the NVM array under the NVMe protocol;

wherein the PMD comprises extended logical blocks to the NVM array under a second protocol; and

a protocol-switching logic configured to direct the processor to:

determine a protocol for use within the device;

wherein if the determined protocol is an NVMe protocol:

PMR usage is determined;

data associated with the PMR is loaded; and

the device is operated under the determined NVMe protocol;

wherein if the determined protocol is a second protocol, the device is operated under the determined second protocol; and

wherein the protocol-switching logic is further configured to initialize the device after determining a protocol.

9. The device of claim 8 , wherein the second protocol is selected from the group consisting of: Peripheral Component Interconnect Express (PCIe), Serial Attached SCSI (SAS), Serial AT Attachment (SATA), Secure Digital (SD), Secure Digital Express (SDX), MultiMediaCard (MMC), and extended MMC (eMMC).

10. The device of claim 8 , wherein the protocol-switching logic is further configured to:

receive an initialization event;

store the PMR data into the NVM array; and

initialize the device.

11. The device of claim 8 , wherein the protocol-switching logic is further configured to:

receive a power cycle event;

store the PMR data into the NVM array; and

power down the device.

12. A device, comprising:

a processor;

a memory comprising a Persistent Memory Region (PMR) configured to operate under multiple protocols through a single interface wherein a first protocol is a Non-Volatile Memory Express (NVMe) protocol and a second protocol is a Secure Digital Express (SDX) protocol; and

a protocol-switching logic configured to direct the processor to:

initialize the device; and

determine a protocol for use with the device:

wherein if the determined protocol is an NVMe protocol:

a PMR usage threshold is determined;

data associated with the PMR is loaded; and

the device is operated under the determined NVMe protocol;

wherein if the determined protocol is an SDX protocol, the PMR is operated under the SDX protocol;

wherein the PMR is configured to provide performance enhancements under the SDX protocol;

wherein the device is configured to physically couple with multiple host-computing devices; and

wherein the device is further configured to be hot-swappable between multiple host-computing devices.

13. The device of claim 12 , wherein the determination of a protocol occurs in response to coupling the device to a new host-computing device.

14. The device of claim 13 , wherein the determination of the protocol can occur by analyzing data transferred on one or more data channels.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 057651 FRAME 0296 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058981/0958 →
SECURITY INTEREST Recorded Sep 17, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 057651/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2021
From: SREEDHAR, PRADEEP; MUTHIAH, RAMANATHAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 056489/0875 →
Cited By (1)
US 12,475,068