Granted Patent B2

US 10,394,706 · App. 15/802,257 · Granted Aug 27, 2019

Abstract

Claims (30)

1. An apparatus, comprising:

a set of non-volatile memory cells; and

one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to receive a plurality of non-sequential memory access commands directed to the set of non-volatile memory cells and predict a memory access command based on the plurality of non-sequential memory access commands according to a model obtained from a training set of non-sequential memory access commands, the one or more control circuits are configured to access the set of non-volatile memory cells according to the memory access command.

2. The apparatus of claim 1 wherein the plurality of non-sequential memory access commands include read commands, the memory access command is a read command directed to a predicted address, and the one or more control circuits are configured to read data from the predicted address prior to receiving a read command directed to the predicted address.

3. The apparatus of claim 2 wherein the one or more control circuits include a read cache configured to maintain the data from the predicted address until the memory access command is received.

4. The apparatus of claim 1 wherein the plurality of non-sequential memory access commands include write commands, the memory access command is a write command directed to a predicted address, and the one or more control circuits are configured to defer writing one or more portions of data received with the write commands until the write command is received with corresponding data.

5. The apparatus of claim 4 wherein the one or more control circuits include a write cache configured to maintain the one or more portions of data received with the write commands until the write command is received with corresponding data, the one or more control circuits are further configured to write the one or more portions of data and the corresponding data in the set of non-volatile memory cells together after the write command is received with the corresponding data.

6. The apparatus of claim 1 wherein the set of non-volatile memory cells form a plurality of blocks, a block is a unit of erase, the plurality of non-sequential memory access commands include write commands, the memory access command is a write command directed to a predicted address, and the one or more control circuits are configured to maintain an open location to write data with the predicted address in a block of the plurality of blocks, the block containing data that is logically associated with the predicted address.

7. The apparatus of claim 6 wherein the block is an open block containing data with addresses that are sequential with the predicted address.

8. The apparatus of claim 7 wherein the one or more control circuits are configured to maintain a plurality of open blocks, each open block containing data that is logically associated with one or more predicted addresses.

9. The apparatus of claim 1 wherein the one or more control circuits are configured to record the plurality of memory access commands and update the model according to the plurality of memory access commands.

10. The apparatus of claim 1 wherein the model is obtained through multiple regression cycles comparing predicted memory access commands with received memory access commands for one or more test sets of non-sequential memory access commands.

11. The apparatus of claim 1 wherein the set of non-volatile memory cells are monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate.

12. The apparatus of claim 11 wherein the set of non-volatile memory cells are arranged in NAND strings that extend vertically through the one or more physical levels of arrays of memory cells.

13. A method, comprising:

generating predicted memory access commands from a plurality of non-sequential memory access commands according to a model;

comparing the predicted memory access commands from the model with memory access commands received to determine accuracy of the predicted memory access commands according to the model; and

in response to determining that accuracy of the predicted memory access commands according to the model is above a threshold, accessing a non-volatile memory according to predictions of the model.

14. The method of claim 13 further comprising, in response to determining that accuracy of the predicted memory access commands according to the model is below a threshold, modifying the model and repeating the generating and the comparing to determine accuracy of predicted memory access commands according to the model as modified.

15. The method of claim 14 further comprising repeating the modifying, the generating, and the comparing, in a number of iterations to improve the model.

16. The method of claim 15 further comprising, in response to determining that accuracy of the predicted memory access commands according to the model is below a threshold after a predetermined number of iterations, accessing the non-volatile memory without using the model.

17. The method of claim 13 wherein accessing the non-volatile memory according to predictions of the model includes prefetching data from the non-volatile memory according to predicted read commands predicted by the model.

18. The method of claim 13 wherein accessing the non-volatile memory according to predictions of the model includes deferring writing of portions of received data to the non-volatile memory according to predicted write commands predicted by the model so that the portions of received data can be written in together with additional data received with the predicted write commands predicted by the model.

19. An apparatus, comprising:

a set of non-volatile memory cells;

means for generating a machine learning model to predict memory access commands from a plurality of received memory access commands;

means for generating predicted read and write commands for the set of non-volatile memory cells from a plurality of non-sequentially received read and write commands according to the machine learning model; and

means for accessing the set of non-volatile memory cells according to the predicted read and write commands prior to receiving the predicted read and write commands.

20. The apparatus of claim 19 further comprising:

means for testing the machine learning model to determine accuracy of the machine learning model.

Assignments (10)