IP Library Granted Patent US 10,528,506
Granted Patent B2
US 10,528,506 · App. 15/786,763 · Granted Jan 7, 2020

Uniform performance monitor for a data storage device and method of operation

Inventors: Avichay Haim Hodes (Kfar Ben Nun, IL); Judah Gamliel Hahn (Ofra, IL)
Assignee: Western Digital Technologies, Inc.
G06F13/385G06F3/0653G06F3/0656G06F3/0659G06F13/1673G06F13/4027G06F3/0689
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Quick Facts
Patent No.
US 10,528,506
App. No.
15/786,763
Granted
Jan 7, 2020
Kind
B2
Abstract

An apparatus includes a first interface configured to receive a first message from a host device or from a data storage device. The apparatus further includes a buffer and a second interface. The buffer is coupled to the first interface and is configured to store the first message. The second interface is coupled to the buffer and is configured to provide the first message to the data storage device or to the host device, respectively. The second interface is further configured to provide, at a time based on a performance metric associated with the first message, a second message to the data storage device or to the host device, respectively. The apparatus further includes a circuit configured to determine the performance metric.

Claims (47)

1. An apparatus comprising:

a first interface configured to receive a first message from a host device or from a data storage device;

a buffer coupled to the first interface and configured to store the first message;

a second interface coupled to the buffer and configured to:

provide the first message to the data storage device or to the host device, respectively; and

provide, at a delayed time based on a performance metric associated with the first message, a second message to the data storage device or to the host device, respectively, wherein the performance metric is a per-command latency of the data storage device; and

a circuit configured to:

determine the performance metric; and

determine the delayed time of the second message to the data storage device or to the host device, respectively, by the second interface in response to determining that the per-command latency of the first message is less than a threshold, thereby increasing per-command latency of the data storage device to a target latency.

2. The apparatus of claim 1 , wherein the threshold is stored in a configuration register that is pre-set at a factory.

3. The apparatus of claim 2 , wherein the circuit is further configured to insert at least one no-operation (NOOP) command at the buffer to delay providing the second message to the data storage device or to the host device, respectively.

4. The apparatus of claim 1 , further comprising a timer configured to determine a time interval associated with the first message.

5. The apparatus of claim 4 , wherein the per-command latency of the first message is obtained from the time interval.

6. The apparatus of claim 1 , wherein the circuit is further configured to delay providing of the second message to the data storage device or to the host device, respectively, to thereby reduce per-command latency differences between the data storage device and one or more additional data storage devices.

7. The apparatus of claim 1 , wherein the circuit is configured to determine an additional performance metric that is equal to a throughput associated with the first message.

8. The apparatus of claim 1 , wherein the circuit comprises a counter circuit configured to determine a number of messages stored at the buffer.

9. The apparatus of claim 8 , wherein the circuit is further configured to determine the performance metric in response to determining that the number exceeds one.

10. The apparatus of claim 1 , further comprising a plurality of buffers that includes the buffer and at least one other buffer, wherein:

the buffer is associated with a first operation type; and

the at least one other buffer is associated with a second operation type that is different than the first operation type.

11. The apparatus of claim 10 , wherein the circuit is further configured to assign the first message to the buffer in response to determining that an opcode of the first message indicates the first operation type.

12. The apparatus of claim 10 , wherein the circuit is further configured to assign the first message to the buffer in response to determining, based on a first logical address of the first message and at least one other logical address of at least one other message, that the first message is associated with the first operation type.

13. The apparatus of claim 10 , wherein:

the first operation type corresponds to one of a sequential read type, a random read type, a sequential write type, or a random write type; and

the second operation type corresponds to another of the sequential read type, the random read type, the sequential write type, or the random write type.

14. The apparatus of claim 1 , wherein the first interface is further configured to receive the first message from the host device.

15. The apparatus of claim 1 , wherein the first interface is further configured to receive the first message from the data storage device.

16. A method comprising:

storing, at a buffer of a bridge device connected to a first data storage device, a first message from a host device or from the first data storage device;

providing the first message from the bridge device to the first data storage device or to the host device, respectively;

determining a performance metric associated with the first message, wherein the performance metric is a per-command latency of the first data storage device; and

providing, at a delayed time based on the per-command latency being less than a threshold, a second message to the first data storage device or to the host device, respectively, to thereby increase per-command latency of the first data storage device to a target latency and reduce differences between the first data storage device and at least a second data storage device of a group of storage devices that are in communication with the host device.

17. The method of claim 16 , further comprising delaying providing the second message to the first data storage device or to the host device, respectively, in response to determining that the performance metric satisfies a threshold, wherein delaying providing the second message to the first data storage device comprises inserting at least one no-operation (NOOP) command in the buffer.

18. The method of claim 17 , further comprising:

periodically sampling input/output (I/O) traffic, the I/O traffic including the first message;

splitting the I/O traffic into workloads;

classifying the workloads;

in response to a queue depth of the buffer exceeding a particular value, determining whether a throughput satisfies a throughput threshold; and

in response to the queue depth failing to exceed the particular value, determining whether a per-command latency is less than a latency threshold,

wherein the second message is delayed in response to the per-command latency being less than the latency threshold.

19. A bridge device comprising:

means for receiving, at the bridge device configured to connect to a first data storage device, a first message from a host device or from the first data storage device;

means for storing the first message at the bridge device;

means for determining a per-command latency associated with the first message;

means for providing the first message from the bridge device to the first data storage device or to the host device, respectively; and

means for providing, at a delayed time based on the per-command latency being less than a threshold, a second message to the first data storage device or to the host device, respectively, to thereby increase per-command latency of the first data storage device to a target latency and reduce differences, including per-command latency differences, between the first data storage device and at least a second data storage device of a group of storage devices that are in communication with the host device.

20. The bridge device of claim 19 , further comprising means for determining a time interval associated with the first message.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2017
From: HODES, AVICHAY HAIM; HAHN, JUDAH GAMLIEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 044222/0458 →
Continuity (1)
Related Publication 20190114276A1 · Apr 18, 2019