Apparatus with a memory controller configured to control access to randomly accessible non-volatile memory
View Patent ↗An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.
1. An apparatus, comprising:
a mother board;
a plurality of processors coupled to the mother board;
an interconnect fabric coupled to the plurality of processors and the mother board;
a first controller means for controlling a first memory channel, the first controller means being distinct from the plurality of processors;
a second controller means for controlling a second memory channel, the second controller means being distinct from the plurality of processors and the first controller means;
one or more DRAM DIMMS coupled to the first controller means and the first memory channel, wherein the first controller means controls the one or more DRAM DIMMS; and
one or more non-DRAM DIMMS coupled to the second controller means and the second memory channel, wherein the second controller means controls the one or more non-DRAM DIMMS, wherein the first controller means, the second controller means, the one or more DRAM DIMMS and the one or more non-DRAM DIMMS are coupled to the motherboard.
2. The apparatus of claim 1 , wherein the one or more DRAM DIMMS comprises a plurality of DRAM DIMMS.
3. The apparatus of claim 2 , wherein the one or more non-DRAM DIMMS comprises a plurality of non-DRAM DIMMS.
4. The apparatus of claim 3 , further comprising a plurality of traces coupled between the plurality of DRAM DIMMS and the first controller means.
5. The apparatus of claim 4 , further comprising a plurality of traces coupled between the plurality of non-DRAM DIMMS and the second controller means.
6. The apparatus of claim 1 , wherein the first memory channel is parallel to the second memory channel.
7. The apparatus of claim 1 , wherein the one or more DRAM DIMMS are plugged into one or more sockets disposed in the first memory channel, and wherein the one or more non-DRAM DIMMS are plugged into one or more sockets disposed in the second memory channel.
8. The apparatus of claim 1 , wherein the plurality of processors are coupled to the motherboard through a plurality of processor sockets.
9. An apparatus, comprising:
a mother board;
one or more first processors coupled to the mother board, wherein the one or more first processors include:
processor elements; and
first controller means for controlling read and write access to DRAM memory modules, wherein the DRAM memory modules are coupled to a first memory channel;
a second processor coupled to the mother board, the second processor being distinct from the one or more first processors, wherein the second processor includes:
a processor element; and
second controller means for controlling read and write access to non-DRAM memory modules, wherein the non-DRAM memory modules are coupled to a second memory channel; and
an interconnect fabric coupled to the one or more first processors, the second processor and the mother board.
10. The apparatus of claim 9 , wherein the one or more first processors is coupled to a plurality of DRAM memory modules.
11. The apparatus of claim 10 , wherein the second processor is coupled to a plurality of DRAM memory modules.
12. The apparatus of claim 11 , wherein the second processor is also coupled to a plurality of non-DRAM memory modules.
13. The apparatus of claim 12 , wherein the second processor further includes third controller means for controlling read and write access to DRAM memory modules.
14. An apparatus, comprising:
one or more DRAM memory modules coupled to a first memory channel;
one or more non-DRAM memory modules coupled to a second memory channel;
first controller means for controlling read and write access to the one or more DRAM memory modules, the first controller means is coupled to the one or more DRAM memory modules;
second controller means for controlling read and write access to the one or more non-DRAM memory modules, the second controller means is coupled to the one or more non-DRAM memory modules, wherein the second controller means is distinct from the first controller means; and
a third controller means for controlling access to the first controller means and the second controller means, the third controller means is coupled to the first controller means and the second controller means, wherein the third controller means is distinct from the first controller means and the second controller means.
15. The apparatus of claim 14 , further comprising an edge connector.
16. The apparatus of claim 14 , further comprising third controller means for controlling read and write access to one or more additional DRAM memory modules, the third controller means is coupled to the one or more additional DRAM memory modules.
17. The apparatus of claim 14 , wherein the one or more DRAM memory modules comprises a plurality of DRAM memory modules.
18. The apparatus of claim 17 , wherein the one or more non-DRAM memory modules comprises a plurality of non-DRAM memory modules.
19. The apparatus of claim 18 , further comprising a plurality of traces coupled between the plurality of DRAM memory modules and the first controller means.
20. The apparatus of claim 19 , further comprising a plurality of traces coupled between the plurality of non-DRAM memory modules and the second controller means.