Devices and methods for decoupling of physical layer
A device with a physical layer (PHY) core component, a PHY I/O component, a decoupling I/O component, and a decoupling core component, where the PHY core component is adjacent to the PHY I/O component, the PHY I/O component is adjacent to the decoupling I/O component, the decoupling I/O component is adjacent to the decoupling core component and is positioned a first distance away from the PHY core component, and the decoupling core component is adjacent to an edge of the device and is positioned a second distance away from the PHY core component.
1. A device, comprising:
a physical layer (PHY) core component;
a PHY input/output (I/O) component;
a decoupling I/O component; and
a decoupling core component, wherein:
the PHY core component is adjacent to the PHY I/O component,
the PHY I/O component is adjacent to the decoupling I/O component,
the decoupling I/O component is adjacent to the decoupling core component and is positioned a first distance away from the PHY core component, and
the decoupling core component is adjacent to an edge of the device and is positioned a second distance away from the PHY core component.
2. The device of claim 1 , wherein the device comprises a System-on-Chip (SOC) logic device.
3. The device of claim 1 , wherein the decoupling core component is positioned on an edge of the device a non-zero distance away from the PHY core component.
4. The device of claim 1 , wherein the decoupling core component is positioned on a same surface of the device and a non-zero distance away from the PHY core component.
5. The device of claim 1 , wherein the decoupling core component is positioned within a component different than the PHY core component.
6. The device of claim 1 , wherein:
the PHY core component is logically coupled to the PHY I/O component and the decoupling core component,
the PHY core component is electrically isolated from the PHY I/O component, the decoupling I/O component, and the decoupling core component,
the PHY I/O component is electrically coupled to the decoupling I/O component, and
the decoupling core component is electrically isolated from the PHY I/O component and the decoupling I/O component.
7. A device, comprising:
a physical layer (PHY) core component;
a system-on-chip core logic component;
an input/output (I/O) component;
a decoupling I/O component;
a decoupling core component; and
means for operating a logic circuit, wherein:
the PHY core component is electrically coupled to the system-on-chip core logic component,
the system-on-chip core logic component is logically coupled to the I/O component,
the PHY core component is electrically isolated from the I/O component, the decoupling I/O component
the I/O component is electrically coupled to the decoupling I/O component,
the PHY core component is electrically coupled to the decoupling core component, and
the decoupling core component is electrically isolated from the I/O component and the decoupling I/O component.
8. The device of claim 7 , wherein the decoupling core component is located on a substrate of the device different than that of the PHY core component.
9. The device of claim 7 , wherein the decoupling core component is comprised of metal-oxide-metal capacitors.
10. The device of claim 7 , wherein the decoupling core component is positioned on a same surface of the device and a non-zero distance away from the PHY core component.
11. The device of claim 7 , wherein the decoupling core component is positioned within a component different than the PHY core component.
12. The device of claim 7 , wherein the decoupling core component is positioned on an edge of the device a non-zero distance away from the PHY core component.
13. A method of configuring a logic circuit, comprising:
positioning a physical layer (PHY) core component onto the logic circuit;
positioning a system-on-chip core logic component onto the logic circuit;
positioning a PHY input/output (I/O) component adjacent to the PHY core component;
positioning a decoupling I/O component adjacent to the PHY I/O component and a first distance away from the PHY core component; and
positioning a decoupling core component adjacent to an edge of the logic circuit and a second distance away from the PHY core component, wherein:
the PHY core component is electrically coupled to the system-on-chip core logic component,
the system-on-chip core logic component is logically coupled to the I/O component,
the PHY core component is electrically isolated from the I/O component and the decoupling I/O component
the I/O component is electrically coupled to the decoupling I/O component,
the PHY core component is electrically coupled to the decoupling core component, and
the decoupling core component is electrically isolated from the I/O component and the decoupling I/O component.
14. The method of claim 13 , wherein the decoupling core component is located on a substrate of the logic circuit different than that of the PHY core component.
15. The method of claim 13 , wherein the decoupling core component is comprised of one or more of metal-oxide-metal capacitors and MOS capacitors.
16. The method of claim 13 , wherein the decoupling core component is located at an edge of the logic circuit a non-zero distance away from the PHY core component.
17. A system, comprising:
a physical layer (PHY) core component;
a PHY input/output (I/O) component;
a decoupling I/O component; and
a decoupling core component, wherein:
the decoupling core component is adjacent to an edge of a logic circuit assembly,
the decoupling I/O component is adjacent to the decoupling core component,
the PHY I/O component is adjacent to the decoupling I/O component and spaced a first distance from the edge of the logic circuit assembly, and
the PHY core component is adjacent to the PHY I/O component and spaced a second distance from the edge of the logic circuit assembly.
18. The system of claim 17 , wherein the decoupling core component is positioned a non-zero distance away from the PHY core component.
19. The system of claim 17 , wherein the decoupling core component is positioned on a same surface of the logic circuit assembly and a non-zero distance away from the PHY core component, and is located on a substrate of the logic circuit assembly different than that of the PHY core component.
20. The system of claim 17 , wherein:
the PHY core component is logically coupled to the PHY I/O component and the decoupling core component,
the PHY core component is electrically isolated from the PHY I/O component and the decoupling I/O component,
the PHY I/O component is electrically coupled to the decoupling I/O component, and
the decoupling core component is electrically isolated from the PHY I/O component and the decoupling I/O component.
21. The system of claim 17 , wherein the decoupling core component is comprised of metal-oxide-metal capacitors.
22. A system, comprising:
a host device; and
a logic circuit coupled to the host device, the logic circuit comprising:
a physical layer (PHY) core component;
a system-on-chip core logic component;
an input/output (I/O) component;
a decoupling I/O component; and
a decoupling core component, wherein:
the decoupling core component is spaced a first distance from the decoupling I/O component, and
the system-on-chip core logic component is spaced a second distance from the decoupling core component.
23. The system of claim 22 , wherein the decoupling core component is positioned on an edge of the logic circuit a non-zero distance away from the PHY core component.
24. The system of claim 22 , wherein the decoupling core component is positioned on a same surface of the logic circuit and a non-zero distance away from the PHY core component.
25. The system of claim 22 , wherein:
the PHY core component is electrically coupled to the system-on-chip core logic component,
the system-on-chip core logic component is logically coupled to the I/O component,
the PHY core component is electrically isolated from the I/O component and the decoupling I/O component,
the I/O component is electrically coupled to the decoupling I/O component,
the PHY core component is electrically coupled to the decoupling core component, and
the decoupling core component is electrically isolated from the I/O component and the decoupling I/O component.
26. The system of claim 22 , wherein the decoupling core component is located on a substrate of the logic circuit different than that of the PHY core component.
27. The system of claim 22 , wherein the decoupling core component is comprised of metal-oxide-metal capacitors.