Data receiver design in DDR memory interfaces
Systems and methods disclosed herein provide for reducing noise on an data signal at receiving devices. Systems and methods disclosed herein are suited for opening a data eye by reducing noise, such as inter-symbol interference. An example of the systems and methods disclosed herein include a first equalization circuit that receives an input data signal and applies amplification to the input data signal, and a second equalization that adjusts a first pulse of the first compensated data signal based on a subset of pulses that preceded the first pulse in the first compensated data signal. In an illustrative example, the first equalization circuit can be provided as a continuous time linear equalization (CTLE) that apply a fixed boost and adjustable gain to the input data signal, and the second equalization circuit can be provided as a multi-path decision feedback equalization (DFE).
1. A compensation circuit for improving a data eye of an input data signal, the compensation circuit comprising:
an input/output (I/O) terminal configured to detect the input data signal from a channel, the input data signal comprising a plurality of consecutive pulses representative of a data pattern encoded on the input data signal and inter-symbol interference (ISI) between the plurality of consecutive pulses;
a first equalization circuit having a first input terminal that receives the input data signal from the I/O terminal and an output terminal that provides a first compensated data signal, the first equalization circuit configured to apply amplification to the input data signal as the first compensated data signal; and
a second equalization circuit connected to an output terminal of the first equalization circuit, the second equalization circuit configured to reduce the ISI on the first compensated data signal and output a second compensated data signal by adjusting a first pulse of the plurality of consecutive pulses based on a subset of pulses of the plurality of consecutive pulses that are sequentially prior to the first pulse.
2. The compensation circuit of claim 1 , wherein amplification applied to the input data signal comprises a fixed boost component and an adjustable gain component.
3. The compensation circuit of claim 2 , wherein the adjustable gain component is adjustable between a upper gain and a lower gain, and wherein the fixed boost component is less than the upper gain.
4. The compensation circuit of claim 1 , wherein the first equalization circuit comprises a continuous time linear equalization (CTLE) circuit, the CTLE circuit comprising the first input terminal, a second input terminal connected to a reference signal, and the output terminal.
5. The compensation circuit of claim 4 , wherein the CTLE circuit is configured to generate a transfer function that inverts a frequency response of the channel, apply the transfer function to the input data signal, and output the first compensated data signal on the output terminal.
6. The compensation circuit of claim 1 , wherein the second equalization circuit is configured to generate feedback current based on the subset of pulses and apply the feedback current to the first compensated data signal and reduce the ISI on the first compensated data signal.
7. The compensation circuit of claim 1 , wherein the subset of pulses comprises four pulses of the plurality of consecutive pulses that are prior to the first pulse.
8. The compensation circuit of claim 1 , wherein the second equalization circuit is a multi-data path decision feedback equalization (DFE) circuit, the multi-data path DFE comprises a first data path including a first slicer circuit and a first plurality of flip-flop circuits and a second data path including a second slicer circuit and a second plurality of flip-flop circuits.
9. The compensation circuit of claim 8 , wherein the first data path is configured to detect even bits of the data pattern from even pulses of the plurality of consecutive pulses, and the second data path is configured to detect odd bits of the data pattern from odd pulses of the plurality of consecutive pulses, wherein the second equalization circuit is configured to: reduce ISI on the even pulses of the first compensated data signal based on the detected even bits, and reduce ISI on the odd pulses of the first compensated data signal based on the detected odd bits.
10. A method for improving a data eye of an input data signal, the method comprising:
detecting the input data signal on a channel, the input data signal comprising a plurality of consecutive pulses representative of a data pattern encoded on the input data signal and inter-symbol interference (ISI) between the plurality of consecutive pulses;
supplying a first compensated data signal by applying amplification to the input data signal by a first equalization circuit;
reducing, by a second equalization circuit, the ISI on the first compensated data signal by adjusting a first pulse of the plurality of consecutive pulses based on a subset of pulses of the plurality of consecutive pulses that are sequentially prior to the first pulse; and
outputting a second compensated data signal as the first compensated data signal with the reduced ISI.
11. The method of claim 10 , wherein applying amplification to the input data signal comprises: applying a fixed boost component and an adjustable gain component to the input data signal.
12. The method of claim 11 , wherein the adjustable gain component is adjustable between a upper gain and a lower gain, and wherein the fixed boost component is less than the upper gain.
13. The method of claim 10 , wherein the first equalization circuit comprises a continuous time linear equalization (CTLE) circuit.
14. The method of claim 13 , further comprising:
generating a transfer function by the CTLE circuit that inverts a frequency response of the channel;
applying the transfer function to the input data signal; and
outputting the first compensated data signal to the second equalization circuit.
15. The method of claim 10 , further comprising:
generating, by the second equalization circuit, feedback current based on the subset of pulses; and
applying the feedback current to the first compensated data signal to reduce the ISI on the first compensated data signal.
16. The method of claim 10 , wherein the subset of pulses comprises four pulses of the plurality of consecutive pulses that are prior to the first pulse.
17. The method of claim 10 , wherein the second equalization circuit is a multi-data path decision feedback equalization (DFE) circuit, the multi-data path DFE comprises a first data path including a first slicer circuit and a first plurality of flip-flop circuits and a second data path including a second slicer circuit and a second plurality of flip-flop circuits.
18. The method of claim 17 , further comprising:
detecting even bits of the data pattern from even pulses of the plurality of consecutive pulses on the first data path;
detecting odd bits of the data pattern from odd pulses of the plurality of consecutive pulses on the second data path; and
reducing ISI on the even pulses of the first compensated data signal based on the detected even bits, and reducing ISI on the odd pulses of the first compensated data signal based on the detected odd bits.
19. An receiver circuit comprising:
an input/output (I/O) pad that receives an input data signal transmitted over a channel, the input data signal is encoded with a data pattern comprising a plurality of bits;
a termination circuit connected to the I/O pad that detects a plurality of first pulses on the input data signal, wherein each first pulse is representative of a bit of the plurality of bits;
a continuous time linear equalization (CTLE) circuit connected to an output of the termination circuit and receives the plurality of first pulses, the CTLE circuit applies amplification to the plurality of first pulses to generate a plurality of second pulses, the amplification having a fixed boost component and an adjustable gain component; and
a multi-path decision feedback equalization (DFE) circuit connected to an output of the CTLE circuit and receives the plurality of second pulses, the multi-path DFE circuit generates a feedback current for a first pulse of the plurality of second pulses based on a subset of the plurality of second pulses that preceded the first pulse, and applies the feedback current to the first pulse to reduce noise on the input data signal due to the channel.
20. The receiver circuit of claim 19 , wherein the multi-path DFE circuit comprises:
a first data path that detects a subset of even bits of the plurality of bits from the plurality of second pulses;
a second data path that detects a subset of odd bits of the plurality of bits from the plurality of second pulses; and
a summer circuit configured to apply the feedback current to the first pulse,
wherein, in a case where the first pulse corresponds to an even bit, the feedback current is generated based on the subset of the subset of even bits, and
wherein in a case where the first pulse corresponds to an odd bit, the feedback current is generated based on the subset of the subset of odd bits.