Patent Assignment
Reel/Frame 065656/0649
PATENT COLLATERAL AGREEMENT- A&R
Recorded: 2023-11-21
Received: 2023-11-21
Pages: 35
Assignor
WESTERN DIGITAL TECHNOLOGIES, INC.
Executed: 2023-11-17
Assignee
JPMORGAN CHASE BANK, N.A.
10 SOUTH DEARBORN, CHICAGO, IL, 60603, UNITED STATES
Covered Applications
(100)
MEDIA UNDERLAYER STRUCTURE FOR HEAT-ASSISTED MAGNETIC RECORDING AND MEDIA FABRICATION METHODS THEREFOR
App. No. 18/383,638
→
MICRO SOLDER JOINT AND STENCIL APERTURE DESIGN
App. No. 18/493,379
→
THREE-DIMENSIONAL MEMORY DEVICE WITH DIFFERENT WIDTH SUPPORT PILLAR STRUCTURES AND METHODS OF MAKING THE SAME
App. No. 18/493,036
→
SUPPRESSION OF PEAK ICC DURING BLOCK SELECTION IN NON-VOLATILE MEMORIES
App. No. 18/492,545
→
DEVICES AND METHODS FOR METAL ORGANIC FRAMEWORK (MOF) BASED OXYGEN REPLENISHMENT IN DATA STORAGE DEVICES
App. No. 18/492,559
→
SELECTABLE LOW POWER MODE FOR STORAGE DEVICES
App. No. 18/491,540
→
METAL LINES LOCATED BETWEEN ETCH STOP LAYERS AND SEPARATED BY AIR GAPS AND METHODS OF FORMING THE SAME
App. No. 18/491,297
→
READ RECOVERY WITH TIME LIMIT IN NONVOLATILE MEMORY
App. No. 18/490,782
→
POLE TIP RECESSION COMPENSATION BY DUAL HEATER RATIO OPTIMIZATION IN A HARD DISK DRIVE
App. No. 18/490,225
→
Read-Protected Storage Device With Sequential Logging
App. No. 18/490,364
→
Bandwidth Averaging In A Stochastic System
App. No. 18/489,555
→
SSD Optimization Awareness To Atomicity Of Different System Files
App. No. 18/489,560
→
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SLOPING WORD LINES FOR STAIRLESS CONTACT AND METHODS OF FORMING THE SAME
App. No. 18/488,360
→
IMPROVED HOST DRAM AND PCIE BANDWIDTH UTILIZATION FOR DRAM-LESS DEVICES
App. No. 18/488,421
→
Write Protect HW Acceleration
App. No. 18/488,426
→
MAGNETIC RECORDING MEDIUM WITH MAGNESIUM-TITANIUM OXIDE (MTO) LAYER FORMED USING PULSED DIRECT CURRENT SPUTTER DEPOSITION
App. No. 18/379,410
→
FLEXIBLE PRINTED CIRCUIT FINGER LAYOUT FOR LOW CROSSTALK
App. No. 18/379,587
→
INCREASED VCM CURRENT RESOLUTION DURING TRACK FOLLOW TO DECREASE NRRO
App. No. 18/485,622
→
Smart Host Stream Release
App. No. 18/485,070
→
Erase Type Detection Mechanism
App. No. 18/485,050
→
DATA TRANSFER FOR VEHICLES
App. No. 18/485,140
→
DARK LASER HEATING BY POSITIVE PULSE BIASING IN HEAT ASSISTED MAGNETIC RECORDING
App. No. 18/483,595
→
SUSPENSION LOAD BEAM RAIL-BASED GIMBAL LIMITER
App. No. 18/378,400
→
Adaptive Tuning Of Memory Device Clock Rates Based On Usage Workloads
App. No. 18/483,488
→
ARTIFICIAL SELECT GATE CUT FOR NAND
App. No. 18/482,996
→
READ IN MULTI-TIER NON-VOLATILE MEMORY
App. No. 18/483,010
→
Multiple Command Format Interpretation For SSD
App. No. 18/377,821
→
Shortened Commands To Reduce Data Transmission
App. No. 18/377,820
→
READ FOR MEMORY CELL WITH THRESHOLD SWITCHING SELECTOR
App. No. 18/482,538
→
DATA STORAGE DEVICE SORTING ACCESS COMMANDS BASED ON PERFORMANCE AND OFF-TRACK MITIGATION OPTIMIZATION
App. No. 18/377,666
→
NON-VOLATILE MEMORY WITH CURRENT DETECTION CIRCUIT
App. No. 18/481,786
→
KEY-GROUP BASED DATA MANAGEMENT IN KV SSD
App. No. 18/480,671
→
ALIGNMENT TOOL FOR A SOLDER MACHINE
App. No. 18/480,724
→
Data Storage Device and Method for Delaying Execution of a Host Write Command to Perform an Internal Memory Operation
App. No. 18/376,122
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PHOSPHORUS-DOPED SILICON OXIDE ION-GETTERING STRUCTURES AND METHODS OF FORMING THE SAME
App. No. 18/479,432
→
THREE-DIMENSIONAL MEMORY DEVICES INCLUDING SELF-ALIGNED SOURCE-CHANNEL JUNCTIONS AND METHODS FOR FORMING THE SAME
App. No. 18/479,457
→
CAPILLARY FOR A WIRE BONDING MACHINE HAVING A DYNAMICALLY ADJUSTABLE CHAMFER DIAMETER
App. No. 18/478,358
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LATERALLY UNDULATING ISOLATION TRENCHES AND METHODS OF MAKING THE SAME
App. No. 18/477,907
→
ENABLING POWER OPTIMIZATION THROUGH DRAM BANK MANAGEMENT IN SOLID STATE DRIVES
App. No. 18/373,403
→
TRENCH PATTERNING PROCESS USING MICROCRACKING
App. No. 18/475,826
→
VOICE COIL MOTOR COMPOSITE MAGNET ASSEMBLY INCLUDING LOW-COERCIVITY MAGNETIC MATERIAL
App. No. 18/373,957
→
PROVIDING HOST WITH MULTIPLE MAPPING INFORMATION THAT SPAN ACROSS MULTIPLE HPB REGIONS
App. No. 18/372,805
→
HARD DISK DRIVE SLIDER COATING FOR SUSPENSION MECHANICAL IMPROVEMENT
App. No. 18/373,034
→
CONTROLLING INPUT/OUTPUT PAD DISCHARGE RATE IN STORAGE DEVICES
App. No. 18/372,777
→
METHOD AND SYSTEM FOR HANDLING HOST COMMANDS OVERLAPPING WITH DEFERRED UNMAP ADDRESS RANGES IN STORAGE DEVICES
App. No. 18/372,759
→
METHOD FOR HANDLING EXTREME TEMPERATURES IN STORAGE DEVICES
App. No. 18/372,152
→
SCHEDULING EXECUTION OF COMMANDS IN A DATA STORAGE DEVICE BASED ON COMMAND PARAMETERS
App. No. 18/473,774
→
MANAGING STREAMS BASED ON PREDICTED HOST COMMANDS
App. No. 18/473,500
→
THREE-DIMENSIONAL MEMORY DEVICE WITH ISOLATION TRENCH FILL STRUCTURE HAVING LATERALLY-UNDULATING SIDEWALLS AND METHOD OF MAKING THE SAME
App. No. 18/471,896
→
POWER IMPROVEMENT FOR MINIMUM SWITCHING FREQUENCY OPERATION
App. No. 18/471,405
→
WORD LINE ZONE BASED UNSELECT WORD LINE BIAS TO ENABLE SINGLE-SIDE GATE-INDUCED DRAIN LEAKAGE ERASE
App. No. 18/371,100
→
NON-VOLATILE MEMORY WITH SEQUENTIAL READ
App. No. 18/471,455
→
Tape Heads Having Shifted Array/Pad Arrangements
App. No. 18/370,273
→
NEIGHBOR PLANE DISTURB (NPD) DETECTION FOR MEMORY DEVICES
App. No. 18/369,296
→
STAIR-STEP CONFIGURATION FOR A SEMICONDUCTOR DIE OF AN INTEGRATED CIRCUIT
App. No. 18/468,904
→
NON-VOLATILE MEMORY WITH EFFICIENT PRECHARGE IN SUB-BLOCK MODE
App. No. 18/468,349
→
TOUCHDOWN DETECTION AND WRITE-SPACING SETTING IN MAGNETIC RECORDING HEADS WITH PROTRUDING FEATURES
App. No. 18/468,448
→
THRESHOLD VOLTAGE BUDGET BY EMPLOYING AN OXIDE-NITRIDE PITCH DEPENDENT THRESHOLD VOLTAGE WINDOW
App. No. 18/369,028
→
BIT LINE TIMING BASED CELL TRACKING QUICK PASS WRITE FOR PROGRAMMING NON-VOLATILE MEMORY APPARATUSES
App. No. 18/368,951
→
Spin-Orbit Torque SOT Reader with Recessed Spin Hall Effect Layer
App. No. 18/368,220
→
DATA PATH OSCILLATOR MISMATCH ERROR REDUCTION FOR NON-VOLATILE MEMORY
App. No. 18/467,005
→
DC AND SYNCHRONIZED ENERGY ASSISTED PERPENDICULAR MAGNETIC RECORDING (EPMR) DRIVER CIRCUIT FOR HARD DISK DRIVE (HDD)
App. No. 18/467,045
→
Non-localized Spin Valve Multi-Free-Layer Reader Hybridized with Spin Orbit Torque Layers
App. No. 18/367,882
→
Non-localized Spin Valve Reader Hybridized with Spin Orbit Torque Layer
App. No. 18/367,877
→
APPARATUS AND METHODS FOR BACK-TO-BACK STATE MACHINE CONTROLLER BUS OPERATIONS
App. No. 18/466,085
→
SEMICONDUCTOR DEVICE FABRICATION METHOD USING A DEPOSITION APPARATUS WITH A CONTOURED WAFER CARRIER RING
App. No. 18/466,108
→
BACK GRINDING TAPE HAVING TABS TO ASSIST IN REMOVING THE BACK GRINDING TAPE FROM A WAFER
App. No. 18/464,779
→
Multi-Tier Error Correction Codes for DNA Data Storage
App. No. 18/464,494
→
Topological Insulator Based Spin Torque Oscillator Reader
App. No. 18/244,555
→
Cache Writing to Zones to Maximize Write Bandwidth
App. No. 18/464,503
→
BLOCK DATA ENCRYPTION OF NON-VOLATILE MEMORY THROUGH SELECTIVE SELECT GATE ERASE THROUGH CHARGE COUPLED SCHEME
App. No. 18/463,525
→
LOCATION-BASED MAINTENANCE OPERATIONS FOR A DATA STORAGE DEVICE
App. No. 18/463,506
→
MEMORY DIE STACK HAVING A SWITCH FOR SELECTIVELY CONNECTING A MEMORY DIE TO A SUBSTRATE
App. No. 18/463,805
→
CHEMICAL MECHANICAL POLISHING PROCESS USING STEAM FOR POLISHING FLUID DELIVERY AND AN APPARATUS FOR IMPLEMENTING THE SAME
App. No. 18/462,830
→
MEMORY DEVICE INCLUDING WORD LINE CONTACT STRIPS AND METHODS OF FORMING THE SAME
App. No. 18/462,955
→
PROGRAMMING TECHNIQUES TO IMPROVE ERASE STATE UPPER TAILS IN A MEMORY DEVICE
App. No. 18/243,314
→
HMB Random and Sequential Access Coherency Approach
App. No. 18/461,777
→
OPTIMIZED ERRATIC PROGRAM DETECTION PROCESS
App. No. 18/242,793
→
DFL TDMR Middle Shield Throat Height Control for Improved Stability
App. No. 18/243,053
→
FAIRNESS AND CONSISTENCY IN MULTI-FUNCTION NONVOLATILE MEMORY (NVM) EXPRESS (NVMe) DEVICE (MFND)
App. No. 18/461,779
→
RESOURCE ALLOCATION TO AVOID COMMAND TIMEOUTS IN A STORAGE DEVICE
App. No. 18/461,939
→
CREDIT ALLOCATION FOR ENABLING ACCESS TO HARDWARE RESOURCES OF A COMPUTING DEVICE
App. No. 18/461,089
→
MEMORY TESTING FLOW SET UP WITH COMPUTATIONAL INTELLIGENCE
App. No. 18/461,237
→
Data Storage Device and Method for Predicting Future Read Thresholds
App. No. 18/242,061
→
TEMPERATURE CONTROL OF A LASER DIODE BY APPLYING REVERSE BIAS IN A DATA STORAGE DEVICE CONFIGURED FOR HEAT-ASSISTED MAGNETIC RECORDING
App. No. 18/460,376
→
THREE-DIMENSIONAL MEMORY DEVICE WITH PILLAR SHAPED TRENCH BRIDGE STRUCTURES AND METHODS OF FORMING THE SAME
App. No. 18/459,938
→
TRAINING ENSEMBLE MODELS TO IMPROVE PERFORMANCE IN THE PRESENCE OF UNRELIABLE BASE CLASSIFIERS
App. No. 18/459,320
→
Multi-Layer NFT for HAMR with a Thermal Shunt Connecting the Metal Layers
App. No. 18/241,164
→
STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE WITH LAYER CONTACT VIA STRUCTURES LOCATED ABOVE SUPPORT PILLAR STRUCTURES AND METHODS OF FORMING THE SAME
App. No. 18/457,883
→
Data Storage Device and Method for Inferring a Read Threshold Using a Time Tag Determination
App. No. 18/239,302
→
UNSINGULATED SEMICONDUCTOR PACKAGE
App. No. 18/456,906
→
INTERPOSER FOR TROUBLESHOOTING A BALL GRID ARRAY (BGA) DEVICE AND COUPLING THE BGA DEVICE TO A PRINTED CIRCUIT BOARD WITH LIMITED HEAT EXPOSURE
App. No. 18/238,952
→
DYNAMICALLY DETERMINING A RATIO OF MEMORY BLOCKS TO INCLUDE IN A GARBAGE COLLECTION PROCESS
App. No. 18/456,856
→
PHY LANES DISABLING FOR POWER EFFICIENCY
App. No. 18/455,958
→
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME
App. No. 18/455,988
→
STAGED HIGH-DENSITY BACKPLANE FOR ELECTRONIC MODULES
App. No. 18/237,556
→
NON-VOLATILE MEMORY BITMAP FOR GARBAGE COLLECTION
App. No. 18/454,253
→
ERROR HANDLING IN ASYMMETRIC SUB-BLOCKS
App. No. 18/237,041
→
METHOD FOR OPTIMIZING LOGICAL-TO-PHYSICAL TABLE UPDATES FOR FIXED GRANULARITY LOGICAL-TO-PHYSICAL TABLES
App. No. 18/237,301
→
RECLAIM PACKAGE CACHE FOR THERMAL THROTTLING
App. No. 18/237,096
→