IP Library Granted Patent US 12,573,456
Granted Patent B2
US 12,573,456 · App. 18/371,100 · Granted Mar 10, 2026

Word line zone based unselect word line bias to enable single-side gate-induced drain leakage erase

Inventors: Abhijith Prakash (Milpitas, CA); Xiang Yang (Santa Clara, CA)
Assignee: Sandisk Technologies, Inc.
G11C16/16G11C16/0433G11C16/08
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Quick Facts
Patent No.
US 12,573,456
App. No.
18/371,100
Granted
Mar 10, 2026
Kind
B2
Abstract

Embodiments disclosed herein are directed to performing a single-side gate-induced drain leakage (GIDL) erase operation. Control circuitry may be configured to perform a single-side GIDL erase operation on a memory block in which a selected sub-block is erased while an unselected sub-block is not erased. During the single-side GIDL erase operation, the control circuitry may be configured to apply a first unselect bias voltage to a first set of word lines of the unselected sub-block, where the first set of word lines is associated with a first word line zone and the first word line zone is associated with an unselect bias voltage, and apply a second unselect bias voltage to a second set of word lines of the unselected sub-block, where the second set of word lines is associated with a second word line zone and the second word line zone is associated with another unselect bias voltage.

Claims (31)

1 . A memory device, comprising:

a memory block including a plurality of sub-blocks, wherein the memory block has a tiered arrangement in which the plurality of sub-blocks includes sub-blocks in different tiers, each of the plurality of sub-blocks including a plurality of word lines; and

control circuitry configured to perform a single-side gate-induced drain leakage (GIDL) erase operation on the memory block in a sub-block mode in which a selected sub-block of the plurality of sub-blocks in the memory block is erased while an unselected sub-block in a first tier of the plurality of sub-blocks in the memory block is not erased, the control circuitry further configured to, during the single-side GIDL erase operation:

apply a first unselect bias voltage to a first set of word lines of the unselected sub-block in the first tier, wherein the first set of word lines is associated with a first word line zone of a plurality of word line zones, and wherein each word line zone of the plurality of word line zones is associated with an unselect bias voltage; and

apply a second unselect bias voltage to a second set of word lines of the same unselected sub-block in the first tier, wherein the second set of word lines is associated with a second word line zone of the plurality of word line zones,

wherein the first word line zone is associated with a first memory hole diameter of the unselected sub-block, the second word line zone is associated with a second memory hole diameter of word lines in the unselected sub-block, and the first memory hole diameter is less than the second memory hole diameter.

2 . The memory device of claim 1 , the control circuitry further configured to:

identify a word line zone of the plurality of word line zones corresponding to a set of word lines; and

set an unselect bias voltage related parameter corresponding to the set of word lines based on the identified word line zone.

3 . The memory device of claim 1 , wherein the first unselect bias voltage is more positive than the second unselect bias voltage.

4 . The memory device of claim 1 , wherein the second unselect bias voltage is more negative than the first unselect bias voltage.

5 . A method of operating a non-volatile semiconductor memory device, the method comprising:

performing a single-side gate-induced drain leakage (GIDL) erase operation on a memory block in a sub-block mode in which a selected sub-block of a plurality of sub-blocks in the memory block is erased while an unselected sub-block in a first tier of the plurality of sub-blocks in the memory block is not erased, wherein the memory block has a tiered arrangement in which the plurality of sub-blocks includes sub-blocks in different tiers; and

during the single-side GIDL erase operation:

applying a first unselect bias voltage to a first set of word lines of the unselected sub-block in the first tier, the first set of word lines associated with a first word line zone of a plurality of word line zones, each word line zone of the plurality of word line zones associated with an unselect bias voltage; and

applying a second unselect bias voltage to a second set of word lines of the same unselected sub-block in the first tier, the second set of word lines associated with a second word line zone of the plurality of word line zones.

6 . The method of claim 5 , the method further comprising:

identifying a word line zone of the plurality of word line zones corresponding to a set of word lines; and

setting an unselect bias voltage related parameter corresponding to the set of word lines based on the identified word line zone.

7 . The method of claim 5 , wherein the first unselect bias voltage is more positive than the second unselect bias voltage.

8 . The method of claim 5 , wherein the second unselect bias voltage is more negative than the first unselect bias voltage.

9 . An apparatus, comprising:

a memory block including a plurality of sub-blocks, wherein the memory block has a tiered arrangement in which the plurality of sub-blocks includes sub-blocks in different tiers,

each of the plurality of sub-blocks including a plurality of word lines; and

a means for performing a single-side gate-induced drain leakage (GIDL) erase operation on the memory block in a sub-block mode in which a selected sub-block of the plurality of sub-blocks in the memory block is erased while an unselected sub-block in a first tier of the plurality of sub-blocks in the memory block is not erased, the means for performing the single-side GIDL erase operation being configured to, during the single-side GIDL erase operation:

apply a first unselect bias voltage to a first set of word lines of the unselected sub-block in the first tier, the first set of word lines associated with a first word line zone of a plurality of word line zones, each word line zone of the plurality of word line zones associated with an unselect bias voltage; and

apply a second unselect bias voltage to a second set of word lines of the same unselected sub-block in the first tier, the second set of word lines associated with a second word line zone of the plurality of word line zones.

10 . The apparatus of claim 9 , the means for performing the single-side GIDL erase operation being further configured to:

identify a word line zone of the plurality of word line zones corresponding to a set of word lines; and

set an unselect bias voltage related parameter corresponding to the set of word lines based on the identified word line zone.

11 . The apparatus of claim 9 , wherein the first unselect bias voltage is more positive than the second unselect bias voltage.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2023
From: PRAKASH, ABHIJITH; YANG, XIANG
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 065857/0347 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
Continuity (1)
Related Publication 20250104774A1 · Mar 27, 2025
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