IP Library Granted Patent US 12,510,922
Granted Patent B2
US 12,510,922 · App. 18/483,488 · Granted Dec 30, 2025

Adaptive tuning of memory device clock rates based on usage workloads

Inventors: Shay Benisty (Beer Sheva, IL); Ariel Navon (Revava, IL); Alexander Bazarsky (Holon, IL); Dudy David Avraham (Even Yehuda, IL)
Assignee: Sandisk Technologies, Inc.
G06F1/08G06F1/10G06F1/3203
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Quick Facts
Patent No.
US 12,510,922
App. No.
18/483,488
Granted
Dec 30, 2025
Kind
B2
Abstract

Different operations have different clock rate bottleneck points. For example, during a read operation, the processors may be the bottleneck whereas other operations will not be bottlenecks. Those other operations can have their clock rates reduced to save power since there is no benefit to a higher clock rate as the bottleneck is elsewhere. Predicting the bottleneck would be beneficial. Statistics correlating the bottleneck points with the workload and clock rates are tracked. When the workload changes, the statistics can be consulted to determine where the bottleneck is located and then slow down the clock rates for the non-bottleneck operations. A clock rate table is maintained in the device controller. The table holds the clock rate of each component. Predicting the workload and hence, the clock rates, reduces power consumption, improves performance, and better quality of service (QOS) compatibility characteristics.

Claims (40)

1 . A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

define distinct classes of workloads, wherein the distinct classes are characterized by command length diversity level, average or standard deviation (STD) of logical block address (LBA) distance between adjacent commands, average number or STD of consequent write/read commands, and queue depth;

determine a workload for the data storage device;

determine a bottleneck element for the workload;

select a clock rate for the bottleneck element to a maximum clock rate of the bottleneck element; and

select a clock rate for elements other than the bottleneck element to below a maximum clock frequency of the respective elements.

2 . The data storage device of claim 1 , wherein the controller is configured to define multiple combinations of clock rates for the respective elements and the bottleneck element.

3 . The data storage device of claim 1 , wherein the controller is configured to maintain a clock rate table.

4 . The data storage device of claim 1 , wherein the controller is configured to define distinct classes of workloads.

5 . The data storage device of claim 4 , wherein the distinct classes are selected from the group consisting of random read, sequential read, random write, sequential write, mixed workload, and low queue depth.

6 . The data storage device of claim 5 , wherein the distinct classes are characterized by average command size, portion of read commands, write commands, and idle time.

7 . The data storage device of claim 1 , wherein the controller includes a workload analysis module and an adaptive frequency table.

8 . The data storage device of claim 1 , wherein the controller is configured to detect a change in workload.

9 . The data storage device of claim 1 , wherein the controller is configured to monitor impact of clock rate changes.

10 . The data storage device of claim 1 , wherein the clock rates are based on doorbell rates.

11 . The data storage device of claim 10 , wherein the clock rates are additionally based on submission queue statistics maintained by the controller.

12 . A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

classify a current workload of the data storage device;

determine that the current workload is going to switch to a new workload based upon a rate that a doorbell is rung;

track a number of new available commands in each doorbell and an average command size per submission queue; and

select clock rates based upon the new workload from a stored table.

13 . The data storage device of claim 12 , wherein the controller is configured to track the rate that the doorbell is rung.

14 . The data storage device of claim 12 , wherein the controller is configured to predict a pending transfer size for a command in the new workload.

15 . A data storage device, comprising:

means to store data; and

a controller coupled to the means to store data, wherein the controller is configured to:

determine that a current workload is going to switch to a new workload based upon a rate that a doorbell is rung;

determine that the new workload of the data storage device is one of: random read, sequential read, random write, sequential write, and mixed workload;

track a number of new available commands in each doorbell and an average command size per submission queue;

obtain clock rates from a table corresponding to the workload; and

set clock rates for a plurality of components of the data storage device,

wherein the set clock rates are the obtained clock rates.

16 . The data storage device of claim 15 , wherein a clock rate for processors is different from a clock rate for a host interface.

17 . The data storage device of claim 15 , wherein different workloads have different clock rates for one or more components of the plurality of components.

18 . The data storage device of claim 15 , wherein the controller is configured to track the rate that the doorbell is rung.

19 . The data storage device of claim 15 , wherein the controller is configured to predict a pending transfer size for a command in the new workload.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2023
From: BENISTY, SHAY; NAVON, ARIEL; BAZARSKY, ALEXANDER; AVRAHAM, DUDY DAVID
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 065521/0305 →
Continuity (1)
Related Publication 20250117037A1 · Apr 10, 2025
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