MEMORY DIE STACK HAVING A SWITCH FOR SELECTIVELY CONNECTING A MEMORY DIE TO A SUBSTRATE
A memory device includes a stack of memory die packages. Each memory die package includes at least two memory dies. A switch is electrically coupled to at least one of the memory die packages. A bond wire electrically couples the switch to a substrate of the memory device. Each memory die is also electrically coupled to the switch. Based on a received control signal, the switch selects which memory die is electrically and/or communicatively coupled to the substrate using the electrical connections between the memory dies and the bond wire that electrically couples the switch to the substrate.
1 . A memory device, comprising:
a first memory die and a second memory die bonded together to form a first memory die package;
a third memory die and a fourth memory die bonded together to form a second memory die package, the second memory die package and the first memory die package forming a stack of memory die packages;
a switch electrically coupled to a top surface of the first memory die package;
a first electrical connection electrically coupling the first memory die to the switch;
a second electrical connection electrically coupling the second memory die to the switch;
a third electrical connection electrically coupling the third memory die to the switch;
a fourth electrical connection electrically coupling the fourth memory die to the switch; and
a bond wire electrically coupling the switch to a substrate of the memory device.
2 . The memory device of claim 1 , wherein the switch selectively electrically couples one of the first memory die, the second memory die, the third memory die and the fourth memory die to the substrate using the bond wire.
3 . The memory device of claim 1 , further comprising a first pin pad and a second pin pad provided on the top surface of the first memory package, wherein:
the first electrical connection extends from the first pin pad; and
the second electrical connection extends from the second pin pad.
4 . The memory device of claim 3 , further comprising a redistribution layer electrically coupling the second memory die to the second pin pad.
5 . The memory device of claim 1 , wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection and the fourth electrical connection is a bond wire.
6 . The memory device of claim 1 , wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection and the fourth electrical connection is a bond pad.
7 . The memory device of claim 1 , wherein the switch is a multiplexer.
8 . The memory device of claim 1 , further comprising a controller that provides a control signal to the switch, the control signal indicating which of the first memory die, the second memory die, the third memory die and the fourth memory die is electrically coupled to the substrate.
9 . A semiconductor package, comprising:
a first semiconductor die and a second semiconductor die bonded together to form a first package;
a third semiconductor die and a fourth semiconductor die bonded together to form a second package, the second package being stacked with the first package;
a switch electrically coupled to a top surface of the first package;
a plurality of electrical connections electrically coupling the first semiconductor die, the second semiconductor die, the third semiconductor die and the fourth semiconductor die to the switch; and
a bond wire electrically coupling the switch to a substrate.
10 . The semiconductor package of claim 9 , wherein the switch selectively electrically couples one of the semiconductor dies to the substrate using the bond wire.
11 . The semiconductor package of claim 9 , further comprising further comprising a first pin pad and a second pin pad provided on the top surface of the first memory package, wherein:
the first electrical connection extends from the first pin pad; and
the second electrical connection extends from the second pin pad.
12 . The semiconductor package of claim 11 , further comprising a redistribution layer electrically coupling the second memory die to the second pin pad.
13 . The semiconductor package of claim 9 , wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection and the fourth electrical connection is a bond wire.
14 . The semiconductor package of claim 9 , wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection and the fourth electrical connection is a bond pad.
15 . The semiconductor package of claim 9 , wherein the switch is a multiplexer.
16 . The semiconductor package of claim 9 , further comprising a controller that provides a control signal to the switch, the control signal indicating which of the first memory die, the second memory die, the third memory die and the fourth memory die is electrically coupled to the substrate.
17 . A memory device, comprising:
a controller means;
a first semiconductor package having a first semiconductor die bonded with a second semiconductor die;
a second semiconductor package having a third semiconductor die bonded with a fourth semiconductor die, the second semiconductor package and the first semiconductor package arranged in a stacked configuration; and
a switching means electrically coupled to the first semiconductor package and the second semiconductor package, the switching means selectively electrically coupling each of the first semiconductor die, the second semiconductor die, the third semiconductor die and the fourth semiconductor die to a substrate of the memory device using a bond wire that electrically couples the switching means to the substrate.
18 . The memory device of claim 17 , wherein the switching means is electrically coupled to the first semiconductor package using a plurality of bond wires.
19 . The memory device of claim 17 , wherein the switching means is electrically coupled to the first semiconductor package using a plurality of bond pads.
20 . The memory device of claim 17 , wherein the switching means is a multiplexer.