UNSINGULATED SEMICONDUCTOR PACKAGE
An unsingulated semiconductor package includes multiple integrated circuits provided on a single substrate segment and encapsulated by a single cover. The unsingulated semiconductor package is mounted on a PCB of a computing component to increase the capacity and performance capabilities of the computing component without occupying additional space on the PCB.
1 . A computing component, comprising:
a printed circuit board (PCB); and
an unsingulated semiconductor package electrically coupled to the PCB, the unsingulated semiconductor package comprising:
a plurality of integrated circuits provided on an unsingulated substrate segment, the unsingulated substrate segment comprising:
a first substrate segment;
a second substrate segment adjacent the first substrate segment; and
an unsingulated area provided between the first substrate segment and the second substrate segment.
2 . The computing component of claim 1 , wherein the unsingulated substrate segment is associated with a plurality of saw streets.
3 . The computing component of claim 2 , wherein each of the plurality of saw streets have a width between 0.25 millimeters (mm) and 1.3 mm.
4 . The computing component of claim 1 , wherein:
a first integrated circuit of the plurality of integrated circuits is provided on the first substrate segment;
a second integrated circuit of the plurality of integrated circuits is provided on the second substrate segment; and
a third integrated circuit of the plurality of integrated circuits is provided on the unsingulated area.
5 . The computing component of claim 1 , wherein the unsingulated area is associated with a saw street that was skipped during a semiconductor package singulation process.
6 . The computing component of claim 1 , wherein each of the plurality of integrated circuits include one or more semiconductor dies.
7 . The computing component of claim 1 , wherein the plurality of integrated circuits are encapsulated by a single cover.
8 . The computing component of claim 1 , wherein the unsingulated semiconductor package is separated from a plurality of other unsingulated semiconductor packages during a semiconductor package singulation process.
9 . A method, comprising:
assembling a plurality of semiconductor packages on a substrate, wherein:
each semiconductor package includes a plurality of integrated circuits attached to a substrate segment; and
each substrate segment is defined by a plurality of saw streets and includes a first singulation area, a second singulation area and an unsingulated area, wherein a first integrated circuit of the plurality of integrated circuits is adjacent the first singulation area, a second integrated circuit of the plurality of integrated circuits is adjacent the second singulation area and a third integrated circuit of the plurality of integrated circuits is placed on the unsingulated area between the first integrated circuit and the second integrated circuit; and
performing a semiconductor package singulation process to separate each of the plurality of semiconductor packages along each of the plurality of saw streets.
10 . The method of claim 9 , further comprising mounting at least one semiconductor package of the plurality of semiconductor packages on a printed circuit board (PCB).
11 . The method of claim 9 , wherein the unsingulated area is associated with a saw street that was skipped during the semiconductor package singulation process.
12 . The method of claim 11 , wherein the saw street has a width between 0.25 millimeters (mm) and 1.3 mm.
13 . The method of claim 9 , wherein each of the plurality of integrated circuits include one or more semiconductor dies.
14 . A memory device, comprising:
a substrate having at least one saw street that separates the substrate into first and second adjacent sections;
a plurality of memory dies provided on a first surface of the substrate, wherein the plurality of memory dies includes a first memory die mounted on the first section, a second memory die mounted on the second section, and a third memory die mounted in an area between the first and second sections and spanning the at least one saw street;
means for electrically connecting the plurality of memory dies to the substrate;
means for encapsulating the plurality of memory dies; and
external electrical connection means attached to a second surface of the substrate opposing the first surface of the substrate, the external electrical connection means allowing the memory device to be connected to host device.
15 . The memory device of claim 14 , wherein the electrically connecting means comprise bond wires.
16 . The memory device of claim 14 , wherein the at least one saw street has a width between 0.25 millimeters (mm) and 1.3 mm.
17 . The memory device of claim 14 , wherein the memory dies comprise NAND dies.
18 . The memory device of claim 14 , wherein the at least one saw street is a saw street that was skipped during a semiconductor package singulation process.
19 . The memory device of claim 14 , wherein the encapsulating means comprises a mold compound.
20 . The memory device of claim 14 , wherein the external electrical connection means comprises solder balls.