IP Library Granted Patent US 12,457,160
Granted Patent B2
US 12,457,160 · App. 18/489,555 · Granted Oct 28, 2025

Bandwidth averaging in a stochastic system

Inventors: Amir Segev (Meiter, IL); Shay Benisty (Beer Sheva, IL)
Assignee: Sandisk Technologies, Inc.
H04L43/0882H04L47/527
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Quick Facts
Patent No.
US 12,457,160
App. No.
18/489,555
Granted
Oct 28, 2025
Kind
B2
Abstract

Instead of maximizing the possible bandwidth of device, utilize time slice credits (TSC), to ensure bandwidth average over a sliding window. When the average is ensured over a sliding window, the device should not care when the host decides to sample a 100 mSec for example, as the average will always be correct. By utilizing set percentage of predetermined allotment for the average bandwidth requirement, the system can give out credit on a predetermined interval. The credit is given out based on usage and once credit is depleted, data cannot be sent until more credit is accumulated. When data is not sent, the system is given a chance to accumulate credit to increase the amount of data sent. Once credit is at a level high enough to send data the device will send the data, but not at a speed that will surpass the average bandwidth requirement.

Claims (64)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

receive an average bandwidth accuracy requirement;

determine a number of credits to issue to meet the average bandwidth accuracy requirement;

start a timer;

determine that there is any data to send;

determine whether there are sufficient credits available to send the data; and

either:

send the data if the determination is that there are sufficient credits; or

wait for sufficient credits and then send the data, wherein the controller is configured to set the timer for an increment equal to a percentage of a sample size set by a host device, wherein the percentage is equal to the average bandwidth accuracy requirement.

2. The data storage device of claim 1 , wherein the controller is configured to remove credit after sending the data.

3. The data storage device of claim 1 , wherein the controller is configured to add credit to a counter after the timer is incremented for a first segment.

4. The data storage device of claim 1 , wherein the waiting comprises waiting for the timer to expire.

5. The data storage device of claim 4 , wherein the controller is configured to remove all credits from a credit counter when the timer has expired, wherein restart the time when the timer has expired.

6. The data storage device of claim 1 , wherein a total number of credits is insufficient to exceed a higher than average bandwidth on any measured period of time set by a host device.

7. The data storage device of claim 1 , wherein the controller is configured to

initialize a plurality of counters;

fill a first counters of the plurality of counters with credit;

fill a remainder of counters of the plurality of counters with 0 credits;

determine that the credit is insufficient to send data;

accumulate additional credits in the remainder of counters;

determine that there is sufficient credit to send the data, wherein the credit is found in the first counter or any other counters starting with the first counter and up to the remainder of counters;

send the data; and

reduce credit from one or more counters of the plurality of counters.

8. The data storage device of claim 7 , wherein a number of the plurality of counters is equal to 1 divided by a correctness requirement.

9. The data storage device of claim 8 , wherein a sample time period is set by a host device.

10. The data storage device of claim 9 , wherein a correctness requirement is set by the host device.

11. The data storage device of claim 9 , wherein the controller includes a time slide credit module.

12. The data storage device of claim 1 , wherein the controller is configured to:

write data to the memory device;

fetch commands from a host device;

parse the fetched commands;

add credits to a plurality of counters;

subtract credits from the plurality of counters; and

maintain the timer for coordinating the adding and subtracting of credits.

13. The data storage device of claim 12 , wherein the controller is configured to subtract credits from an oldest counter of the plurality of counters when the timer has expired.

14. The data storage device of claim 13 , wherein the controller is configured to generate a new counter with credits when the timer expires, wherein the controller is further configured to restart a counter from the plurality of counters when the counter has expired.

15. The data storage device of claim 1 , wherein the controller is configured to generate a new counter and remove an oldest counter.

16. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

receive an average bandwidth accuracy requirement;

determine a number of credits to issue to meet the average bandwidth accuracy requirement:

start a timer;

determine that there is any data to send;

determine whether there are sufficient credits available to send the data; and

either:

send the data if the determination is that there are sufficient credits; or

wait for sufficient credits and then send the data, wherein the controller is configured to remove credit after sending the data, wherein the credit is removed from an oldest non zero credit counter.

17. The data storage device of claim 16 , wherein the controller is configured to determine which credit counter is an oldest credit counter.

18. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

receive an average bandwidth accuracy requirement;

determine a number of credits to issue to meet the average bandwidth accuracy requirement;

start a timer;

determine that there is any data to send;

determine whether there are sufficient credits available to send the data; and

either:

send the data if the determination is that there are sufficient credits; or

wait for sufficient credits and then send the data, wherein the waiting comprises waiting for the timer to expire, wherein the controller is configured to remove all credits from a credit counter when the timer has expired, wherein restart the time when the timer has expired, wherein the credit counter is an oldest credit counter of a plurality of credit counters.

19. The data storage device of claim 18 , wherein the controller is configured to generate a new counter after removing the oldest credit.

20. The data storage device of claim 19 , wherein the controller is configured to add credit to the new counter.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2023
From: SEGEV, AMIR; BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 065521/0914 →
Continuity (1)
Related Publication 20250133001A1 · Apr 24, 2025
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