DC and synchronized energy assisted perpendicular magnetic recording (EPMR) driver circuit for hard disk drive (HDD)
Various illustrative aspects are directed to a data storage device comprising a storage medium and a head configured to access the storage medium. The head comprises a first write assist element and a second write assist element. Control circuitry for driving the head is configured to apply a first write assist current Im that is synchronized to a write data current Iw to the first write assist element; and to apply a second DC write assist current Imdc to the second write assist element.
1. A data storage device comprising:
a storage medium;
a head configured to write data to the storage medium, the head comprising a first write assist element, a second write assist element, and a write pole; and
control circuitry for driving the head, the control circuitry comprising one or more processing devices that are configured, individually or in combination, to:
apply a write data current (Iw) to the write pole;
apply, to the first write assist element, a first write assist current (Im) that is synchronized to the write data current (Iw); and
apply a second write direct current (DC) assist current (Imdc) to the second write assist element.
2. The data storage device of claim 1 , wherein:
the first write assist element is a field effect energy assisted perpendicular magnetic recording (FEePMR) write assist element that enhances a write field generated by the write pole.
3. The data storage device of claim 2 , wherein the second write assist element is an energy assisted perpendicular magnetic recording (ePMR) write assist element, and wherein, when at least one of the first and second write assist currents is applied to a respective one of the first and the second write assist element, a magnetic field applied to the storage medium increases resulting in one or more of (1) an increase in aerial density of the storage medium, and (2) a reduction in jitter.
4. The data storage device of claim 3 , wherein the control circuitry further comprises:
a first voltage source (Vm) that is coupled to the second write assist element to generate the second DC write assist current (Imdc).
5. The data storage device of claim 1 , wherein the control circuitry further comprises:
a first current source and a second current source that respectively generate first and second toggled currents I_p and I_n, wherein the first and second toggled currents are timed relative to the write data current (Iw), and wherein the first and second current sources are coupled to the first write assist element to generate the first write assist current (Im).
6. The data storage device of claim 1 , wherein the control circuitry further comprises a dynamic wave shaping (DWS) element for programming an overshoot pulse amplitude and an overshoot pulse duration of the first write assist current (Im).
7. The data storage device of claim 1 , wherein the control circuitry further comprises a variable delay element for programming a delay of the first write assist current (Im) relative to the write data current (Iw).
8. The data storage device of claim 1 , wherein the control circuitry further comprises a variable capacitance (Cx) across the first write assist element that sets a rise/fall time of the first write assist current (Im).
9. Control circuitry for driving a head of a data storage device, the head comprising an inductive write assist element and a resistive write assist element, the control circuitry comprising:
means for applying a first write assist current (Im) that is synchronized to a write data current (Iw) to the inductive write assist element; and
means for applying a second DC write assist current (Imdc) to the resistive write assist element.
10. The control circuitry of claim 9 , wherein the means for applying the first write assist current comprises:
means for generating a first toggled current I_p and a second toggled current I_n using a respective one of a first current source and a second current source, wherein the first and second toggled currents are timed relative to the write data current (Iw), and wherein the first and second current sources are coupled to the first write assist element to generate the first write assist current (Im).
11. The control circuitry of claim 9 , wherein the means for applying the second write assist current comprises:
a voltage source (Vm) that is coupled to the second write assist element to generate the second DC write assist current (Imdc).
12. The control circuitry of claim 9 , further comprising a dynamic wave shaping (DWS) element that programs an overshoot pulse amplitude and an overshoot pulse duration of the first write assist current (Im).
13. The control circuitry of claim 9 , further comprising a variable delay element that programs a delay of the first write assist current (Im) relative to the write data current (Iw).
14. The control circuitry of claim 9 , further comprising a variable rise/fall time across the first write assist element that is programmed to set a rise/fall time of the first write assist current (Im).
15. A method for driving a head of a data storage device, the method comprising:
applying a synchronized write assist current (Im) to a field effect energy assisted perpendicular magnetic recording (FEePMR) write assist element during a write operation, wherein the synchronized write assist current (Im) is synchronized to a write data current (Iw);
programming an amplitude and a polarity of the synchronized write assist current (Im) to track an amplitude and a polarity of the write data current (Iw); and
applying a DC write assist current (Imdc) to an ePMR write assist element during the write operation.
16. The method of claim 15 , further comprising:
setting an amplitude and a polarity of the DC write assist current (Imdc) by programming a voltage source (Vm).
17. The method of claim 15 , further comprising:
setting a delay (Td) of the synchronized write assist current (Im) relative to the write data current (Iw) by programming a variable delay element.
18. The method of claim 15 , further comprising:
setting a rise/fall time (Tmr) of the synchronized write assist current (Im) by programming a variable rise/fall current across the FEePMR write assist element.
19. The method of claim 15 , further comprising:
programming an amplitude (Imosa) and a duration (Tosd) of an overshoot pulse for the synchronized write assist current (Im) based on signals from a dynamic wave shaping (DWS) element of the data storage device.
20. A data storage device comprising:
a storage medium;
a head configured to write data to the storage medium, the head comprising a first write assist element and a write pole; and
control circuitry for driving the head, the control circuitry comprising:
a first current source for generating a first toggled current I_p;
a second current source for generating a second toggled current I_n; and
one or more processing devices that are configured, individually or in combination, to:
apply a write data current (Iw) to the write pole;
time the first and second toggled currents relative to the write data current (Iw);
generate a first write assist current (Im), based on coupling the first and second current sources to the first write assist element; and
apply, to the first write assist element, the first write assist current (Im) that is synchronized to the write data current (Iw).
21. A data storage device comprising:
a storage medium;
a head configured to write data to the storage medium, the head comprising a first write assist element and a write pole; and
control circuitry for driving the head, the control circuitry comprising a dynamic wave shaping (DWS) element, and one or more processing devices that are configured, individually or in combination, to:
apply a write data current (Iw) to the write pole;
apply, to the first write assist element, a first write assist current (Im) that is synchronized to the write data current (Iw); and
program, using the DWS element, an overshoot pulse amplitude and an overshoot pulse duration of the first write assist current (Im).
22. A data storage device comprising:
a storage medium;
a head configured to write data to the storage medium, the head comprising a first write assist element and a write pole; and
control circuitry for driving the head, the control circuitry comprising a variable delay element, and one or more processing devices that are configured, individually or in combination, to:
apply a write data current (Iw) to the write pole;
apply, to the first write assist element, a first write assist current (Im) that is synchronized to the write data current (Iw); and
program, using the variable delay element, a delay of the first write assist current (Im) relative to the write data current (Iw).