Optimized erratic program detection process
Embodiments described herein aim to optimize the Erratic Program Detection (EPD) process by eliminating unnecessary operations and adjusting operations that are not optimized for the EPD process. For example, one optimization includes the EPD read operations being performed based on a read mode optimized for faster data retrieval. Further, another optimization includes a first read voltage ramping up at a rate that is faster than a ramp rate used to ramp up a read voltage during performance of a normal read operation. Another optimization also includes a read voltage kick operation between the EPD read operations being eliminated. Finally, another optimization includes parallelizing the scan operation with other ongoing operations.
1. A method for performing erratic program detection, the method comprising the steps of:
programming a plurality of memory cells with different data states; and
subsequent to programming the plurality of memory cells, performing the erratic program detection to identify under-programmed or over-programmed cells of the programmed plurality of memory cells by:
performing a first read operation to detect a first boundary of a region defined between an upper tail of a first data state of the different data states and a lower tail of a second data state of the different data states;
performing a second read operation to detect a second boundary of the region, wherein at least one of the first read operation and the second read operation is performed in a read mode in which first timer values are less than second timer values of a default read mode in which a normal read operation is performed to retrieve data from the memory cells; and
based on results of the first and second read operations, determining if there is overlap between the first data state and the second data state.
2. The method as set forth in claim 1 , further including the step of:
prior to performing the first read operation, ramping up a first read voltage at a ramp rate that is faster than a ramp rate used to ramp up a read voltage during performance of a read operation based on the default read mode.
3. The method as set forth in claim 2 , further including the step of:
prior to performing the second read operation, ramping up a second read voltage at the ramp rate.
4. The method as set forth in claim 1 , wherein the second read operation is performed without performing a read voltage kick operation before the second read operation, the read voltage kick operation including shifting a read voltage from a first level associated with the first read operation to a second level associated with the second read operation.
5. The method as set forth in claim 4 , wherein the second level is a higher value than the first level.
6. The method as set forth in claim 1 , further including the step of:
simultaneously performing a scan operation as the second read operation.
7. A memory device, comprising:
at least one memory block that includes a plurality of memory cells arranged in a plurality of word lines; and
control circuitry configured to program the plurality of memory cells of the at least one memory block with different data states in a plurality of program loops, the control circuitry being configured to:
subsequent to programming the memory cells, performing erratic program detection to identify under-programmed or over-programmed cells of the plurality of memory cells by:
performing a first read operation to detect a first boundary of a region defined between an upper tail of a first data state of the different data states and a lower tail of a second data state of the different data states;
performing a second read operation to detect a second boundary of the region, wherein at least one of the first read operation and the second read operation is performed in a read mode in which first timer values are less than second timer values of a default read mode in which a normal read operation is performed to retrieve data from the memory cells; and
based on results of the first and second read operations, determine if there is overlap between the first data state and the second data state.
8. The memory device as set forth in claim 7 , wherein the control circuitry is further configured to:
prior to performing the first read operation, ramp up a first read voltage at a ramp rate that is faster than a ramp rate used to ramp up a read voltage during performance of a read operation based on the default read mode.
9. The memory device as set forth in claim 8 , wherein the control circuitry is further configured to:
prior to performing the second read operation, ramp up a second read voltage at the ramp rate.
10. The memory device as set forth in claim 7 , wherein the second read operation is performed without performing a read voltage kick operation before the second read operation, the read voltage kick operation including shifting a read voltage from a first level associated with the first read operation to a second level associated with the second read operation.
11. The memory device as set forth in claim 10 , wherein the second level is a higher value than the first level.
12. The memory device as set forth in claim 7 , wherein the control circuitry is further configured to:
simultaneously perform a scan operation as the second read operation.
13. An apparatus, comprising:
at least one memory block that includes a plurality of memory cells arranged in a plurality of word lines with different data states; and
a means for performing an optimized erratic program detection after programming of the plurality of memory cells, the means for performing the optimized erratic program detection being configured to:
subsequent to programming the memory cells, performing erratic program detection to identify under-programmed or over-programmed cells of the plurality of memory cells by:
performing a first read operation to detect a first boundary of a region defined between an upper tail of a first data state of the different data states and a lower tail of a second data state of the different data states;
performing a second read operation to detect a second boundary of the region, wherein at least one of the first read operation and the second read operation is performed in a read mode in which first timer values are less than second timer values of a default read mode in which a normal read operation is performed to retrieve data from the memory cells; and
based on results of the first and second read operations, determine if there is overlap between the first data state and the second data state.
14. The apparatus as set forth in claim 13 , wherein the means for performing the optimized erratic program detection is further configured to:
prior to performing the first read operation, ramp up a first read voltage at a ramp rate that is faster than a ramp rate used to ramp up a read voltage during performance of a read operation based on the default read mode.
15. The apparatus as set forth in claim 14 , wherein the means for performing the optimized erratic program detection is further configured to:
prior to performing the second read operation, ramp up a second read voltage at the ramp rate.
16. The apparatus as set forth in claim 13 , wherein the second read operation is performed without performing a read voltage kick operation before the second read operation, the read voltage kick operation including shifting a read voltage from a first level associated with the first read operation to a second level associated with the second read operation.
17. The apparatus as set forth in claim 16 , wherein the second level is a higher value than the first level.