Memory system and operating method thereof
An operating method of a memory system that includes a plural-level cell memory block capable of storing N-bit data in a single memory cell includes accessing a plural-level cell memory block in an N-bit cell mode, determining a degree of disturbance of the plural-level cell memory block, designating one or more memory cells in an erase state included in an open memory area of the plural-level cell memory block as an M-bit group, where M is an integer smaller than N, according to a result of the determination, and accessing the M-bit group in an M-bit cell mode.
1. An operating method of a memory system that includes a plural-level cell memory block capable of storing N-bit data in a single memory cell, comprising:
accessing a plural-level cell memory block in an N-bit cell mode;
determining a degree of disturbance of the plural-level cell memory block;
designating one or more memory cells in an erase state included in an open memory area of the plural-level cell memory block as an M-bit group, where M is an integer smaller than N, according to a result of the determination; and
accessing the M-bit group in an M-bit cell mode.
2. The operating method of claim 1 , the determining of the degree of disturbance of the accessed plural-level cell memory block includes:
checking whether or not a read count of the memory block exceeds a predetermined threshold value.
3. The operating method of claim 1 , wherein the accessing of the M-bit group in the M-bit cell mode includes:
programming the M-bit group in the M-bit cell mode.
4. The operating method of claim 3 , wherein the programming of the M-bit group in the M-bit cell mode includes:
programming user data in M bits of a plural-level cell.
5. The operating method of claim 4 , wherein the programming of the M-bit group in the M-bit cell mode further includes:
programming dummy data in remaining N-M bits except for the M bits in which the user data is programmed.
6. The operating method of claim 1 , wherein the accessing of the M-bit group in the M-bit cell mode includes:
reading the M-bit group in the M-bit cell mode.
7. The operating method of claim 6 , wherein the reading of the M-bit group in the M-bit cell mode includes:
increasing a read voltage, which distinguishes the erase state and a program state, to read the M-bit group.
8. The operating method of claim 1 , wherein the plural-level cell memory block is a multi-level cell memory block, the M-bit group is a single-level cell group, and the M-bit cell mode is a single-level cell mode.
9. The operating method of claim 1 , wherein the plural-level cell memory block is a triple-level cell memory block, the M-bit group is a single-level cell group, and the M-bit cell mode is a single-level cell mode.
10. The operating method of claim 1 , wherein the plural-level cell memory block is a triple-level cell memory block, the M-bit group is a multi-level cell group, and the M-bit cell mode is a multi-level cell mode.
11. A memory system, comprising:
a memory device including a plural-level cell memory block capable of storing N-bit data in a single memory cell; and
a controller suitable for controlling the memory device,
wherein the controller accesses a plural-level cell memory block in an N-bit cell mode, determines a degree of disturbance of the plural-level cell memory block, designates one or more memory cells in an erase state included in an open memory area of the plural-level cell memory block as an M-bit group, where M is an integer smaller than N, according to a result of the determination, and accesses the M-bit group in an M-bit cell mode (hereinafter referred to as an “M-bit cell mode access”).
12. The memory system of claim 11 , wherein the controller checks whether or not a read count of the memory block exceeds a predetermined threshold value to determine the degree of disturbance of the accessed plural-level cell memory block.
13. The memory system of claim 11 , wherein the M-bit cell mode access includes an M-bit cell mode program operation.
14. The memory system of claim 13 , wherein the controller performs the M-bit cell mode program operation by programming user data in M bits of a plural-level cell.
15. The memory system of claim 14 , wherein the controller performs the M-bit cell mode program operation by programming dummy data in remaining N-M bits except for the M bits in which the user data is programmed.
16. The memory system of claim 11 , wherein the M-bit cell mode access includes an M-bit cell mode read operation.
17. The memory system of claim 16 , wherein the controller increases a read voltage, which distinguishes the erase state and a program state, to read the M-bit group during the M-bit cell mode read operation.
18. The memory system of claim 11 , wherein the plural-level cell memory block is a multi-level cell memory block, the M-bit group is a single-level cell group, and the M-bit cell mode is a single-level cell mode.
19. The memory system of claim 11 , wherein the plural-level cell memory block is a triple-level cell memory block, the M-bit group is a single-level cell group, and the M-bit cell mode is a single-level cell mode.
20. The memory system of claim 11 , wherein the plural-level cell memory block is a triple-level cell memory block, the M-bit group is a multi-level cell group, and the M-bit cell mode is a multi-level cell mode.
21. A memory system, comprising:
a memory device including a plurality of plural-level cell memory blocks, each including a plurality of memory cells, each capable of storing N-bit data; and
a controller suitable for accessing at least one plural-level cell memory block and monitoring disturbance of accessed plural-level cell memory block,
wherein, when the disturbance of the accessed plural-level cell memory block exceeds a threshold value, the controller handles an unprogrammed region of the accessed plural-level cell memory block in a way that one or more memory cells in the unprogrammed region are capable of storing M-bit data, where M is a smaller integer than N.