Method for forming PCM and RRAM 3-D memory cells
View Patent ↗A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4 F 2 . The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.
1. A method of fabricating memory cells, comprising:
depositing onto a substrate a first layer stack, wherein the substrate includes a plurality of selector contacts and wherein the selector contacts have an upper surface;
patterning and etching the first layer stack to form a plurality of word lines and to form a plurality of trenches;
depositing a first insulating layer within the plurality of trenches;
etching a first insulating layer;
depositing a metal within the plurality of trenches;
patterning and etching the metal to form a vertical post and to form a plurality of holes, wherein the vertical posts are disposed on the upper surface of the selector contacts;
depositing a second insulating layer within the plurality of holes;
etching the second insulating layer, wherein the etching is biased towards a side of each of the plurality of holes; and
depositing a conductive material into the plurality of holes.
2. The method of claim 1 , wherein the first insulating layer is deposited onto a first side of a word line and a second side of the word line.
3. The method of claim 2 , wherein the first side of a word line is opposed to the second side of the word line.
4. The method of claim 3 , wherein the first side of a word line and the second side of a word line are facing the plurality of trenches.
5. The method of claim 1 , wherein the first layer stack comprises:
a first insulating layer;
a first memory layer;
a first conductor layer;
a second insulating layer;
a second memory layer; and
a second conductor layer.
6. The method of claim 5 , wherein the first layer stack further comprises: a first hard mask layer.
7. The method of claim 1 , further comprising depositing a second hard mask layer over the metal.
8. A memory device, comprising:
a substrate, wherein the substrate includes a plurality of selector contacts and wherein the selector contacts have an upper surface;
a first layer stack;
a first insulating layer;
a vertical post, wherein the vertical posts are disposed on the upper surface of the selector contacts;
a second insulating layer, wherein the second insulating layer is biased towards a first side of each of the vertical posts, and wherein the second insulating layer has a top surface that is inclined; and
a conductive material, wherein the conductive material is biased towards a second side of each of the vertical posts, wherein the second side is opposite the first side.
9. The memory device of claim 8 , wherein the first layer stack comprises:
a first insulating layer;
a first memory layer;
a first conductor layer;
a second insulating layer;
a second memory layer; and
a second conductor layer.
10. The memory device of claim 9 , wherein the first layer stack further comprises: a hard mask layer.
11. The memory device of claim 8 , wherein the inclined top surface of the second insulating layer is the hypotenuse of a triangle formed by the first side of the vertical post, the substrate, and the top surface of the second insulating layer.
12. The memory device of claim 8 , wherein the first insulating layer is disposed adjacent the vertical posts orthogonal to the second insulating layer.
13. The memory device of claim 8 , further comprising a hard mask layer over the vertical posts.
14. The memory device of claim 8 , wherein the vertical posts are Tungsten.
15. A method of fabricating a plurality of layers of memory cells comprising the steps of: (1) depositing layers of conductive material and insulating material for each layer of memory cells, (2) patterning and etching the layers into a plurality of layers of rows, (3) filling between the plurality of layers of rows with a conductive post material that is electrically insulated from the rows, (4) patterning and etching the conductive post material to form a plurality of conductive posts that are separated by holes, and (5) filling the holes with sidewall liners and conductive materials to form a plurality of memory elements.
16. The method of claim 15 , further comprising the step of electrically connecting a conductive material in a hole with the conductive post material of a conductive post.
17. The method of claim 16 , further comprising cantilevering the substrate during etching to preferentially etch one side of the hole over the opposite side of the hole.
18. The method of claim 15 , further comprising depositing a metal suitable for forming a Resistive RAM.
19. The method of claim 15 , further comprising depositing an oxide suitable for forming a Resistive RAM.
20. The method of claim 15 , further comprising depositing a Chalcogenide alloy suitable for forming a Phase-change memory cell.