IP Library Assignment 046939/0587
Patent Assignment
Reel/Frame 046939/0587

Assignment of Assignor's Interest

Recorded: 2018-08-24 Pages: 8
Assignor
HGST, INC.
Executed: 2018-08-24
Assignee
WESTERN DIGITAL TECHNOLOGIES, INC.
5601 GREAT OAKS PARKWAY, LEGAL DEP./SIMONA BENJAMIN, SAN JOSE, CALIFORNIA, 95119
Covered Properties (76)
Device and Method for Reducing Piracy of Digitized Information
Patent: 6,598,164 →
Application: 09/290,721 →
Low Cost High Density Rectifier Matrix Memory
Patent: 6,956,757 →
Application: 09/887,201 →
Publication: US 2003/0235088
Fabrication of Semiconductor Devices
Patent: 6,586,327 →
Application: 09/965,622 →
Publication: US 2002/0086542
Error Correcting Memory Access Means and Method
Patent: 7,149,934 →
Application: 10/411,594 →
Publication: US 2004/0153944
Fabrication of Semiconductor Devices
Patent: 7,183,206 →
Application: 10/459,699 →
Publication: US 2004/0132288
Scr Matrix Storage Device
Patent: 7,376,008 →
Application: 10/913,218 →
Publication: US 2005/0030810
Low Cost High Density Rectifier Matrix Memory
Patent: 7,460,384 →
Application: 11/229,941 →
Publication: US 2006/0013029
Topography Transfer Method with Aspect Ratio Scaling
Patent: 7,682,981 →
Application: 11/341,953 →
Publication: US 2006/0166508
Error Correcting Memory Access Means and Method
Patent: 8,108,735 →
Application: 11/541,354 →
Publication: US 2007/0028150
Fabrication of Semiconductor Devices
Patent: 7,507,663 →
Application: 11/655,470 →
Publication: US 2007/0117388
Nano-Vacuum-Tubes and Their Application in Storage Devices
Patent: 7,667,996 →
Application: 11/707,739 →
Publication: US 2007/0247890
Memory Array with Readout Isolation
Patent: 7,593,256 →
Application: 11/729,322 →
Publication: US 2007/0230243
Memory Array with Readout Isolation
Patent: 7,548,453 →
Application: 11/729,323 →
Publication: US 2007/0242494
Memory Array with Readout Isolation
Patent: 7,548,454 →
Application: 11/729,423 →
Publication: US 2007/0253234
Low Cost High Density Rectifier Matrix Memory
Patent: 7,826,244 →
Application: 11/780,909 →
Publication: US 2008/0016414
Low Cost High Density Rectifier Matrix Memory
Patent: 7,593,246 →
Application: 11/780,916 →
Publication: US 2008/0013354
Non-Linear Conductor Memory
Patent: 7,813,157 →
Application: 11/926,778 →
Publication: US 2009/0109726
Scr Matrix Storage Device
Patent: 7,652,916 →
Application: 12/107,500 →
Publication: US 2008/0291751
Field-Emitter-Based Memory Array with Phase-Change Storage Devices
Patent: 8,000,129 →
Application: 12/339,696 →
Publication: US 2009/0161420
Diagonal Connection Storage Array
Patent: 8,358,526 →
Application: 12/395,071 →
Publication: US 2009/0219741
Low-Complexity Electronic Circuits and Methods of Forming the Same
Patent: 8,351,238 →
Application: 12/417,245 →
Publication: US 2009/0257269
Method for Forming Self-Aligned Phase-Change Semiconductor Diode Memory
Patent: 8,455,298 →
Application: 12/543,086 →
Publication: US 2010/0047995
Sequencing Decoder Circuit
Patent: 8,325,556 →
Application: 12/575,055 →
Publication: US 2010/0085830
Scr Matrix Storage Device
Patent: 7,916,530 →
Application: 12/633,171 →
Publication: US 2010/0149865
Methods and Apparatus for Disabling a Memory-Array Portion
Patent: 8,325,557 →
Application: 12/639,599 →
Publication: US 2010/0157646
Vertical Switch Three-Dimensional Memory Array
Patent: 8,773,881 →
Application: 12/720,843 →
Publication: US 2010/0232200
Bipolar-Mos Driver Circuit
Patent: 8,035,416 →
Application: 12/827,545 →
Low Cost High Density Rectifier Matrix Memory
Patent: 8,358,525 →
Application: 12/898,205 →
Publication: US 2011/0019455
Diagonally accessed memory array circuit
Patent: 8,635,426 →
Application: 12/925,934 →
Publication: US 2011/0107055
Low-Cost High-Density Rectifier Matrix Memory
Patent: 8,116,109 →
Application: 13/065,755 →
Publication: US 2011/0176349
Means and Method for Operating a Resistive Array
Patent: 8,934,293 →
Application: 13/135,235 →
Ram Memory Device with Nand Type Interface
Patent: 8,537,618 →
Application: 13/199,328 →
Publication: US 2012/0051140
Unified Switch Array for Memory Devices
Patent: 8,378,456 →
Application: 13/199,437 →
Multiple sector parallel access memory array with error correction
Patent: 9,195,540 →
Application: 13/200,909 →
Publication: US 2012/0096331
Bipolar-Mos Driver Circuit
Patent: 8,451,024 →
Application: 13/267,985 →
Publication: US 2012/0086473
Pinched Center Resistive Change Memory Cell
Patent: 8,766,227 →
Application: 13/373,205 →
Scalable Metadata Acceleration with Datapath Metadata Backup
Patent: 8,407,437 →
Application: 13/419,641 →
Low-Complexity Electronic Circuit and Methods of Forming the Same
Patent: 8,526,217 →
Application: 13/692,638 →
Publication: US 2013/0114328
Embedded Non-Volatile Memory
Patent: 8,786,023 →
Application: 13/707,895 →
Publication: US 2014/0158963
Bipolar-MOS Memory Circuit
Patent: 9,007,801 →
Application: 13/714,499 →
Publication: US 2014/0160827
Solid State Devices Having Fine Pitch Structures
Patent: 8,980,532 →
Application: 14/078,769 →
Publication: US 2014/0131830
Vertical Switch Three-Dimensional Memory Array
Patent: 9,305,624 →
Application: 14/282,444 →
Publication: US 2014/0321190
Pinched Center Resistive Change Memory Cell
Patent: 9,070,878 →
Application: 14/283,714 →
Publication: US 2014/0329369
Embedded Non-Volatile Memory
Patent: 9,054,031 →
Application: 14/306,801 →
Publication: US 2014/0335669
Multiple Bit Per Cell Dual-Alloy Gst Memory Elements
Patent: 9,490,426 →
Application: 14/561,679 →
Publication: US 2016/0012889
Operating a Resistive Array
Patent: 9,349,448 →
Application: 14/576,909 →
Publication: US 2015/0155033
Solid State Devices Having Fine Pitch Structures
Patent: 9,437,657 →
Application: 14/616,128 →
Publication: US 2015/0155336
Bipolar-Mos Memory Circuit
Patent: 9,270,269 →
Application: 14/628,925 →
Publication: US 2015/0171864
Controlling Coupling in Large Cross-Point Memory Arrays
Patent: 9,349,447 →
Application: 14/635,532 →
Embedded Non-Volatile Memory
Patent: 9,431,460 →
Application: 14/733,919 →
Publication: US 2016/0020253
Method for Growing a Semiconductor Material on a Crytalline Semeiconductor Substrate
Application: 14/743,132 →
Publication: US 2015/0372226
Self-Aligned Memory Cell Contact
Patent: 9,450,182 →
Application: 14/794,762 →
Publication: US 2016/0020391
Nmos Regulated Voltage Reference
Patent: 9,753,481 →
Application: 14/795,836 →
Publication: US 2016/0124456
Incremental Error Detection and Correction for Memories
Patent: 9,819,365 →
Application: 14/803,091 →
Publication: US 2016/0019112
3-D Planes Memory Device
Patent: 9,679,946 →
Application: 14/835,642 →
Publication: US 2016/0056206
4F2 Scr Memory Device
Patent: 9,871,043 →
Application: 14/841,672 →
Publication: US 2017/0062432
Deposition Method for Planar Surfaces
Patent: 9,837,269 →
Application: 14/956,173 →
Publication: US 2016/0155636
Method for Forming Pcm and Rram 3-D Memory Cells
Patent: 9,570,516 →
Application: 14/967,025 →
Publication: US 2016/0218147
Solid State Devices Having Fine Pitch Structures
Application: 15/181,551 →
Publication: US 2016/0293667
Embedded Non-Volatile Memory
Patent: 9,812,503 →
Application: 15/236,600 →
Publication: US 2016/0351627
Self-Aligned Memory Cell Contact
Application: 15/251,083 →
Publication: US 2016/0372659
Persistent File Handle Object Container Memory Expiry
Application: 15/409,276 →
Publication: US 2018/0203870
Method for Forming Pcm and Rram 3-D Memory Cells
Patent: 9,837,472 →
Application: 15/412,566 →
Publication: US 2017/0133435
Intelligent Flash Architecture
Patent: 9,823,856 →
Application: 15/441,248 →
Dynamic Memory Shrinker for Metadata Optimization
Application: 15/603,414 →
3-D Planes Memory Device
Application: 15/613,842 →
Publication: US 2017/0271407
Scalable and Persistent L2 Adaptive Replacement Cache
Application: 15/626,101 →
Predictable Client Latency Via Background File System Operations
Application: 15/697,152 →
Publication: US 2019/0056871
Predictable Allocation Latency in Fragmented Log Structured File Systems
Application: 15/697,621 →
Publication: US 2019/0057121
Intelligent Redundant Array of Independent Disks
Application: 15/700,912 →
Publication: US 2019/0056865
Incremental Error Detection and Correction for Memories
Application: 15/810,304 →
Publication: US 2018/0069573
Intelligent Redundant Array Of Independent Disks With High Performance Recompaction
Application: 15/887,960 →
Publication: US 2019/0057024
Intelligent Redundant Array Of Independent Disks With Resilvering Beyond Bandwidth Of A Single Drive
Application: 15/887,971 →
Publication: US 2019/0057004
Predictable Client Latency Via Background File System Operations
Application: 62/546,080 →
Predictable Allocation Latency in Fragmented Log Structured File Systems
Application: 62/546,097 →
Intelligent Redundant Array of Independent Disks (iRAID)
Application: 62/546,114 →
Related Assignments (18)
Other recorded transfers of the patents in this record — the chain of ownership.
Release of Security Interest May 15, 2015
From: AMERICAN CAPITAL, LTD.; STILL RIVER FUND III, LIMITED PARTNERSHIP; SARAH G. KURZON 2001 REVOCABLE TRUST; OVONYX, INC.
To: CONTOUR SEMICONDUCTOR, INC.
Reel/Frame 035685/0571 →
Release of Security Interest May 20, 2015
From: AMERICAN CAPITAL, LTD.; STILL RIVER FUND III, LIMITED PARTNERSHIP; SARAH G. KURZON 2001 REVOCABLE TRUST; OVONYX, INC.
To: CONTOUR SEMICONDUCTOR, INC.
Reel/Frame 035749/0956 →
Assignment of Assignor's Interest May 21, 2015
From: CONTOUR SEMICONDUCTOR, INC.
To: HGST NETHERLANDS B.V.
Reel/Frame 035748/0909 →
Corrective Assignment to Correct the Name and Address of the Assignee Previously Recorded on Reel 035748 Frame 0909. Assignor(S) Hereby Confirms the Name and Address of the Assignee Si Hgst, Inc.,3403 Yerba Buena Road,San Jose, Ca 95135. Jun 2, 2015
From: CONTOUR SEMICONDUCTOR, INC.
To: HGST, INC.
Reel/Frame 035831/0594 →
Change of Name Oct 2, 2015
From: NUP2 INCORPORATED
To: CONTOUR SEMICONDUCTOR, INC.
Reel/Frame 036745/0996 →
Assignment of Assignor's Interest Oct 6, 2015
From: CONTOUR SEMICONDUCTOR, INC.
To: HGST, INC.
Reel/Frame 036739/0260 →
Release of Security Interest Oct 7, 2015
From: AMERICAN CAPITAL, LTD.; STILL RIVER FUND III, LIMITED PARTNERSHIP; SARAH G. KURZON 2001 REVOCABLE TRUST; OVONYX, INC.
To: CONTOUR SEMICONDUCTOR, INC.
Reel/Frame 036752/0206 →
Assignment of Assignor's Interest Feb 11, 2016
From: CONTOUR SEMICONDUCTOR, INC.
To: HGST, INC.
Reel/Frame 037713/0545 →
Assignment of Assignor's Interest Jun 7, 2016
From: SHEPARD, DANIEL R.; APODACA, MAC D.; TRENT, THOMAS MICHAEL; HSU, JAMES JUEN
To: CONTOUR SEMICONDUCTOR, INC.
Reel/Frame 038829/0283 →
Security Agreement Jul 19, 2016
From: HGST, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039389/0684 →
Release of Security Interest Aug 16, 2016
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: HGST, INC.
Reel/Frame 039689/0950 →
Assignment of Assignor's Interest Nov 12, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: WODEN TECHNOLOGIES INC.
Reel/Frame 058094/0100 →
Release of Security Interest at Reel 039389 Frame 0684 Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0535 →
Patent Collateral Agreement - a&R Loan Agreement Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
Patent Collateral Agreement - Ddtl Loan Agreement Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
Assignment of Assignor's Interest May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
Change of Name Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
Patent Collateral Agreement Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →