Granted Patent B2

US 7,593,256 · App. 11/729,322 · Granted Sep 22, 2009

Abstract

Claims (38)

1. An information-storage circuit comprising:

a first set of generally parallel conductive lines;

a second set of generally parallel conductive lines that is generally perpendicular to and overlapping with the first set of lines;

a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a nonlinear element bridging a line from the first set of lines and a line from the second set of lines at a region of overlap;

a reference generator for providing a reference value adapted for measurement, the reference value being based at least in part on current flowing through a nonlinear element disposed in at least one of a dummy row or a dummy column; and

state measurement circuitry for determining a selected bit state by comparing the state of a selected bit against the reference value.

2. The circuit of claim 1 wherein the state measurement circuitry measures a charge associated with a selected bit.

3. The circuit of claim 2 further comprising a plurality of capacitances, wherein each measured charge is stored on a capacitance.

4. The circuit of claim 1 further comprising a plurality of capacitances, wherein each capacitance is associated with one of said nonlinear elements.

5. The circuit of claim 4 wherein each capacitance occurs between one of said nonlinear elements and one line selected from said first set of lines or said second set of lines.

6. The circuit of claim 1 further comprising a plurality of capacitances, wherein each capacitance occurs between a first line from said first set of lines and a second line from said second set of lines.

7. The circuit of claim 1 wherein the state measurement circuitry comprises a comparator.

8. The circuit of claim 1 wherein the reference generator is a dummy row circuit.

9. The circuit of claim 1 wherein the reference generator is a dummy column circuit.

10. The circuit of claim 1 wherein the nonlinear element is selected from the group consisting of a diode, a series combination of a diode and a contact opening, and a series combination of a diode and a one-time programmable element.

11. The circuit of claim 1 wherein the state measurement circuitry is off-package.

12. The circuit of claim 1 further comprising a dynamic address decoder for selecting at least one line in the first and second sets of generally parallel conductive lines.

13. A method for determining bit state in an information-storage circuit, the method comprising:

providing a first set of generally parallel conductive lines;

providing a second set of generally parallel conductive lines that is generally perpendicular to and overlapping with the first set of lines;

providing a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a nonlinear element bridging a line from the first set of lines and a line from the second set of lines at a region of overlap;

providing a reference generator for providing a reference value adapted for measurement, the reference value being based at least in part on current flowing through a nonlinear element disposed in at least one of a dummy row or a dummy column; and

providing state measurement circuitry for determining a selected bit state by comparing the state of a selected bit against the reference value.

14. The method of claim 13 wherein determining a selected bit state comprises measuring a charge associated with a selected bit.

15. The method of claim 14 further comprising providing a plurality of capacitances, wherein each measured charge is stored on a capacitance.

16. The method of claim 13 further comprising providing a plurality of capacitances, wherein each capacitance is associated with one of said nonlinear elements.

17. The method of claim 16 wherein each capacitance occurs between one of said nonlinear elements and one line selected from said first set of lines or said second set of lines.

18. The method of claim 13 further comprising providing a plurality of capacitances, wherein each capacitance occurs between a first line from said first set of lines and a second line from said second set of lines.

19. The method of claim 13 wherein comparing the state of the selected bit against the reference value comprises using a comparator.

20. The method of claim 19 wherein the comparator is operated synchronously with the information- storage circuit.

21. The method of claim 19 further comprising detecting a change using the comparator in at least one of charge, voltage and current to determine a digital output state.

22. The method of claim 13 wherein determining the selected bit state comprises determining the presence or absence of a diode.

23. The method of claim 13 wherein determining the selected bit state comprises determining the presence or absence of a series combination of a diode and a contact opening.

24. The method of claim 13 wherein determining the selected bit state comprises determining the presence or absence of a series combination of a diode and a one-time programmable element.

25. The method of claim 13 wherein providing the reference generator comprises providing a dummy row circuit.

26. The method of claim 13 wherein providing the reference generator comprises providing a dummy column circuit.

27. The method of claim 13 wherein the state measurement circuitry is off-package.

28. The method of claim 13 further comprising providing a dynamic address decoder for selecting at least one line in the first and second sets of generally parallel conductive lines.

Assignments (12)