IP Library Assignment 058965/0535
Patent Assignment
Reel/Frame 058965/0535

Release of Security Interest at Reel 039389 Frame 0684

Recorded: 2022-02-08 Pages: 9
Assignor
JPMORGAN CHASE BANK, N.A.
Executed: 2022-02-03
Assignee
WESTERN DIGITAL TECHNOLOGIES, INC.
3355 MICHELSON DRIVE, IRVINE, CALIFORNIA, 92612
Covered Properties (56)
Dual-Addressed Rectifier Storage Device
Patent: 5,889,694 →
Application: 08/863,156 →
Device and Method for Reducing Piracy of Digitized Information
Patent: 6,598,164 →
Application: 09/290,721 →
Dual-Addressed Rectifier Storage Device
Patent: 41,733 →
Application: 09/821,182 →
Low Cost High Density Rectifier Matrix Memory
Patent: 6,956,757 →
Application: 09/887,201 →
Publication: US 2003/0235088
Fabrication of Semiconductor Devices
Patent: 6,586,327 →
Application: 09/965,622 →
Publication: US 2002/0086542
Error Correcting Memory Access Means and Method
Patent: 7,149,934 →
Application: 10/411,594 →
Publication: US 2004/0153944
Fabrication of Semiconductor Devices
Patent: 7,183,206 →
Application: 10/459,699 →
Publication: US 2004/0132288
Data Storage Device, Data Write Method, and Program
Patent: 7,038,870 →
Application: 10/691,757 →
Publication: US 2004/0212910
Scr Matrix Storage Device
Patent: 7,376,008 →
Application: 10/913,218 →
Publication: US 2005/0030810
Low Cost High Density Rectifier Matrix Memory
Patent: 7,460,384 →
Application: 11/229,941 →
Publication: US 2006/0013029
Topography Transfer Method with Aspect Ratio Scaling
Patent: 7,682,981 →
Application: 11/341,953 →
Publication: US 2006/0166508
Error Correcting Memory Access Means and Method
Patent: 8,108,735 →
Application: 11/541,354 →
Publication: US 2007/0028150
Fabrication of Semiconductor Devices
Patent: 7,507,663 →
Application: 11/655,470 →
Publication: US 2007/0117388
Nano-Vacuum-Tubes and Their Application in Storage Devices
Patent: 7,667,996 →
Application: 11/707,739 →
Publication: US 2007/0247890
Memory Array with Readout Isolation
Patent: 7,593,256 →
Application: 11/729,322 →
Publication: US 2007/0230243
Memory Array with Readout Isolation
Patent: 7,548,453 →
Application: 11/729,323 →
Publication: US 2007/0242494
Memory Array with Readout Isolation
Patent: 7,548,454 →
Application: 11/729,423 →
Publication: US 2007/0253234
Dual-Addressed Rectifier Storage Device
Patent: 42,310 →
Application: 11/780,220 →
Publication: US 2008/0013398
Low Cost High Density Rectifier Matrix Memory
Patent: 7,826,244 →
Application: 11/780,909 →
Publication: US 2008/0016414
Low Cost High Density Rectifier Matrix Memory
Patent: 7,593,246 →
Application: 11/780,916 →
Publication: US 2008/0013354
Non-Linear Conductor Memory
Patent: 7,813,157 →
Application: 11/926,778 →
Publication: US 2009/0109726
Scr Matrix Storage Device
Patent: 7,652,916 →
Application: 12/107,500 →
Publication: US 2008/0291751
Low Cost, High-Density Rectifier Matrix Memory
Patent: 7,933,133 →
Application: 12/265,456 →
Publication: US 2009/0225579
Field-Emitter-Based Memory Array with Phase-Change Storage Devices
Patent: 8,000,129 →
Application: 12/339,696 →
Publication: US 2009/0161420
Diagonal Connection Storage Array
Patent: 8,358,526 →
Application: 12/395,071 →
Publication: US 2009/0219741
Low-Complexity Electronic Circuits and Methods of Forming the Same
Patent: 8,351,238 →
Application: 12/417,245 →
Publication: US 2009/0257269
Method for Forming Self-Aligned Phase-Change Semiconductor Diode Memory
Patent: 8,455,298 →
Application: 12/543,086 →
Publication: US 2010/0047995
Sequencing Decoder Circuit
Patent: 8,325,556 →
Application: 12/575,055 →
Publication: US 2010/0085830
Scr Matrix Storage Device
Patent: 7,916,530 →
Application: 12/633,171 →
Publication: US 2010/0149865
Methods and Apparatus for Disabling a Memory-Array Portion
Patent: 8,325,557 →
Application: 12/639,599 →
Publication: US 2010/0157646
Vertical Switch Three-Dimensional Memory Array
Patent: 8,773,881 →
Application: 12/720,843 →
Publication: US 2010/0232200
Bipolar-Mos Driver Circuit
Patent: 8,035,416 →
Application: 12/827,545 →
Low Cost High Density Rectifier Matrix Memory
Patent: 8,358,525 →
Application: 12/898,205 →
Publication: US 2011/0019455
Diagonally accessed memory array circuit
Patent: 8,635,426 →
Application: 12/925,934 →
Publication: US 2011/0107055
Low-Cost High-Density Rectifier Matrix Memory
Patent: 8,116,109 →
Application: 13/065,755 →
Publication: US 2011/0176349
Means and Method for Operating a Resistive Array
Patent: 8,934,293 →
Application: 13/135,235 →
Ram Memory Device with Nand Type Interface
Patent: 8,537,618 →
Application: 13/199,328 →
Publication: US 2012/0051140
Unified Switch Array for Memory Devices
Patent: 8,378,456 →
Application: 13/199,437 →
Multiple sector parallel access memory array with error correction
Patent: 9,195,540 →
Application: 13/200,909 →
Publication: US 2012/0096331
Bipolar-Mos Driver Circuit
Patent: 8,451,024 →
Application: 13/267,985 →
Publication: US 2012/0086473
Pinched Center Resistive Change Memory Cell
Patent: 8,766,227 →
Application: 13/373,205 →
Current steering element formation for memory arrays
Application: 13/385,371 →
Publication: US 2015/0050788
Low-Complexity Electronic Circuit and Methods of Forming the Same
Patent: 8,526,217 →
Application: 13/692,638 →
Publication: US 2013/0114328
Embedded Non-Volatile Memory
Patent: 8,786,023 →
Application: 13/707,895 →
Publication: US 2014/0158963
Bipolar-MOS Memory Circuit
Patent: 9,007,801 →
Application: 13/714,499 →
Publication: US 2014/0160827
Solid State Devices Having Fine Pitch Structures
Patent: 8,980,532 →
Application: 14/078,769 →
Publication: US 2014/0131830
Pinched Center Resistive Change Memory Cell
Patent: 9,070,878 →
Application: 14/283,714 →
Publication: US 2014/0329369
Embedded Non-Volatile Memory
Patent: 9,054,031 →
Application: 14/306,801 →
Publication: US 2014/0335669
Multiple Bit Per Cell Dual-Alloy Gst Memory Elements
Patent: 9,490,426 →
Application: 14/561,679 →
Publication: US 2016/0012889
Operating a Resistive Array
Patent: 9,349,448 →
Application: 14/576,909 →
Publication: US 2015/0155033
Solid State Devices Having Fine Pitch Structures
Patent: 9,437,657 →
Application: 14/616,128 →
Publication: US 2015/0155336
Bipolar-Mos Memory Circuit
Patent: 9,270,269 →
Application: 14/628,925 →
Publication: US 2015/0171864
Embedded Non-Volatile Memory
Patent: 9,431,460 →
Application: 14/733,919 →
Publication: US 2016/0020253
Method for Growing a Semiconductor Material on a Crytalline Semeiconductor Substrate
Application: 14/743,132 →
Publication: US 2015/0372226
Self-Aligned Memory Cell Contact
Patent: 9,450,182 →
Application: 14/794,762 →
Publication: US 2016/0020391
Nmos Regulated Voltage Reference
Patent: 9,753,481 →
Application: 14/795,836 →
Publication: US 2016/0124456
Related Assignments (16)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name Oct 25, 2012
From: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
To: HGST NETHERLANDS B.V.
Reel/Frame 029341/0777 →
Assignment of Assignor's Interest Feb 3, 2016
From: BAKER, R. JACOB; PARKINSON, WARD
To: HGST, INC.
Reel/Frame 037656/0367 →
Security Agreement Jul 19, 2016
From: HGST, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039389/0684 →
Release of Security Interest Aug 16, 2016
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: HGST, INC.
Reel/Frame 039689/0950 →
Assignment of Assignor's Interest Dec 5, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040820/0802 →
Assignment of Assignor's Interest Aug 24, 2018
From: HGST, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046939/0587 →
Security Interest Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
Assignment of Assignor's Interest Nov 12, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: WODEN TECHNOLOGIES INC.
Reel/Frame 058094/0100 →
Release of Security Interest at Reel 052915 Frame 0566 Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
Patent Collateral Agreement - a&R Loan Agreement Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
Patent Collateral Agreement - Ddtl Loan Agreement Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
Assignment of Assignor's Interest May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
Change of Name Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
Patent Collateral Agreement Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
Assignment of Assignor's Interest Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
Security Agreement (Supplemental) Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →