Embedded non-volatile memory
View Patent ↗The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F 2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.
1. A method of fabricating a CMOS logic device incorporating diode-based memory, the method comprising:
forming a layer of gate insulator material over at least a first region of a substrate;
forming a layer of gate electrode material over the gate insulator layer;
over a second region of the substrate, forming a plurality of hollow cups;
after the gate electrode material is formed, forming a memory diode material within the cups;
selectively removing portions of the gate electrode material in the first region to define transistor gate electrodes, source electrodes, and drain electrodes;
depositing a metal over at least some of the gate electrodes, source electrodes, and/or drain electrodes; and
after the memory diode material is formed within the cups, annealing the metal to form silicide transistor contacts.
2. The method of claim 1 , wherein the memory diode material comprises epi-silicon.
3. The method of claim 1 , wherein the memory diode material comprises poly-silicon.
4. The method of claim 1 , further comprising forming an information-storage material over the memory diode material.
5. The method of claim 4 , wherein the information-storage material comprises a phase-change material.
6. The method of claim 5 , wherein the phase-change material comprises a chalcogenide material.
7. The method of claim 5 , wherein the phase-change material comprises at least one of germanium, tellurium, or antimony.
8. The method of claim 1 , further comprising doping the memory diode material via ion implantation.
9. The method of claim 1 , further comprising disposing the CMOS logic device within a package.
10. The method of claim 9 , wherein the package is removable from and interchangeable among a plurality of electronic systems.