Multiple bit per cell dual-alloy GST memory elements
View Patent ↗In various embodiments, a memory cell for storing two or more bits of information includes two series-connected memory storage elements composed of programmable materials having different melting points, enabling independent programming of the storage elements via different current pulses.
1. A method of programming a memory cell comprising (i) a first storage element comprising a first programmable material having a first melting point, and (ii) in series with the first storage element, a second storage element comprising a second programmable material having a second melting point less than the first melting point, the method comprising:
applying a first current pulse to the memory cell to reset both the first and second storage elements, the first current pulse comprising (i) a first maximum current for heating the first and second storage elements above the first melting point, and (ii) a first trailing edge portion decreasing from the first maximum current sufficiently rapidly to quench each of the first and second programmable materials in a first bit state;
applying a second current pulse to the memory cell to set both the first and second storage elements, the second current pulse comprising (i) a second maximum current for heating the first and second storage elements above the first melting point, and (ii) a second trailing edge portion decreasing from the second maximum current sufficiently slowly to anneal each of the first and second programmable materials in a second bit state different from the first bit state;
applying a third current pulse to the memory cell to set the first storage element and reset the second storage element, the third current pulse comprising (i) a third maximum current for heating the first and second storage elements above the first melting point, (ii) a third trailing edge portion decreasing from the third maximum current to a first intermediate current sufficiently slowly to anneal the first programmable material in the second bit state, the second programmable material remaining substantially melted thereduring, and (iii) a fourth trailing edge portion decreasing from the first intermediate current sufficiently rapidly to quench the second programmable material in the first bit state, wherein the third current pulse has an amplitude that melts both the first and second storage elements; and
applying a fourth current pulse to the memory cell to reset the first storage element and set the second storage element, the fourth current pulse comprising (i) a fourth maximum current for heating the first and second storage elements above the first melting point, (ii) a fifth trailing edge portion decreasing from the fourth maximum current to a second intermediate current sufficiently rapidly to quench the first programmable material in the first bit state, the second programmable material remaining substantially melted thereduring, and (iii) a sixth trailing edge portion decreasing from the second intermediate current sufficiently slowly to anneal the second programmable material in the second bit state.
2. The method of claim 1 , wherein the first bit state corresponds to a substantially amorphous microstructure.
3. The method of claim 1 , wherein the second bit state corresponds to a substantially crystalline microstructure.
4. The method of claim 1 , wherein each of the first and second programmable materials comprises a chalcogenide material.
5. A memory cell comprising:
a first storage element comprising a first programmable material having a first melting point; and
in series with the first storage element, a second storage element comprising a second programmable material having a second melting point less than the first melting point,
wherein the memory cell is programmable by:
applying a first current pulse to the memory cell to reset both the first and second storage elements, the first current pulse comprising (i) a first maximum current for heating the first and second storage elements above the first melting point, and (ii) a first trailing edge portion decreasing from the first maximum current sufficiently rapidly to quench each of the first and second programmable materials in a first bit state,
applying a second current pulse to the memory cell to set both the first and second storage elements, the second current pulse comprising (i) a second maximum current for heating the first and second storage elements above the first melting point, and (ii) a second trailing edge portion decreasing from the second maximum current sufficiently slowly to anneal each of the first and second programmable materials in a second bit state different from the first bit state,
applying a third current pulse to the memory cell to set the first storage element and reset the second storage element, the third current pulse comprising (i) a third maximum current for heating the first and second storage elements above the first melting point, (ii) a third trailing edge portion decreasing from the third maximum current to a first intermediate current sufficiently slowly to anneal the first programmable material in the second bit state, the second programmable material remaining substantially melted thereduring, and (iii) a fourth trailing edge portion decreasing from the first intermediate current sufficiently rapidly to quench the second programmable material in the first bit state, wherein the third current pulse has an amplitude that melts both the first and second storage elements, and
applying a fourth current pulse to the memory cell to reset the first storage element and set the second storage element, the fourth current pulse comprising (i) a fourth maximum current for heating the first and second storage elements above the first melting point, (ii) a fifth trailing edge portion decreasing from the fourth maximum current to a second intermediate current sufficiently rapidly to quench the first programmable material in the first bit state, the second programmable material remaining substantially melted thereduring, and (iii) a sixth trailing edge portion decreasing from the second intermediate current sufficiently slowly to anneal the second programmable material in the second bit state.
6. The memory cell of claim 5 , wherein the first bit state corresponds to a substantially amorphous microstructure.
7. The memory cell of claim 5 , wherein the second bit state corresponds to a substantially crystalline microstructure.
8. The memory cell of claim 5 , wherein each of the first and second programmable materials comprises a chalcogenide material.
9. The memory cell of claim 5 , wherein the first storage element is disposed above the second storage element, and further comprising, disposed below the second storage element, a selection device for selecting the memory cell.
10. The memory cell of claim 9 , wherein the selection device comprises a diode.
11. The memory cell of claim 5 , further comprising, connected in series with the first and second storage elements, a third storage element comprising a third programmable material having a third melting point different from at least one of the first or second melting points.