Low-complexity electronic circuit and methods of forming the same
View Patent ↗An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.
1. A memory device comprising:
a memory array comprising a plurality of generally parallel rows and a plurality of generally parallel columns intersecting the plurality of rows;
a memory cell proximate an intersection of a row and a column, the memory cell comprising a resistive-change material; and
control circuitry electrically connected to the memory array, the control circuitry comprising a plurality of MOS transistors,
wherein (i) all of the MOS transistors of the control circuitry are of the same type, the type selected from the group consisting of PMOS and NMOS, and (ii) the control circuitry comprises at least one latch.
2. The memory device of claim 1 , wherein the resistive-change material comprises a chalcogenide alloy.
3. The memory device of claim 2 , wherein the chalcogenide alloy comprises at least one of germanium, antimony, or tellurium.
4. The memory device of claim 1 , wherein the memory cell comprises a current-steering element.
5. The memory device of claim 4 , wherein the resistive-change material and current steering element are connected in series.
6. The memory device of claim 4 , wherein the current-steering element comprises a diode.
7. The memory device of claim 1 , wherein the control circuitry comprises a sequencer.
8. The memory device of claim 1 , wherein the control circuitry comprises a sequencer and a decoder, wherein the sequencer is addressable.
9. The memory device of claim 8 , wherein the decoder comprises an array of diodes.
10. The memory device of claim 1 , wherein the memory device is contained within a package.
11. The memory device of claim 10 , wherein the package is removable to another device.
12. The memory device of claim 10 , wherein the package is embedded within another device.
13. The memory device of claim 10 , wherein the package has an industry standard form factor.
14. The memory device of claim 13 , wherein the industry standard form factor is selected from the group consisting of Compact Flash, Secure Digital, MultiMedia Card, PCMCIA Card, and Memory Stick.
15. The memory device of claim 10 , wherein the package comprises at least one additional device therewithin.
16. The memory device of claim 15 , wherein the at least one additional device is selected from the group consisting of a memory device, a controller, a logic device, a micro-controller, a microprocessor, a controller chip, and a chip-set.
17. The memory device of claim 10 , wherein the package has a type which is selected from the group consisting of Ball Grid Array, Dual In-Line Package (DIP), SOIC, PLCC, or TQFP.
18. The memory device of claim 1 , wherein the memory device comprises at least one of (i) one or more layers of storage cells or (ii) one or more layers of storage elements.
19. The memory device of claim 1 , wherein the memory device comprises one or more sub-arrays or tiles.
20. The memory device of claim 1 , wherein the memory cells store one or more pieces of digital information selected from the group consisting of text, books, music, audio, photography, video, cartography, and maps.