Granted Patent B2

US 9,007,801 · App. 13/714,499 · Granted Apr 14, 2015

Abstract

Claims (13)

1. An integrated electronic memory device comprising control logic and one or more cross point information storage arrays wherein:

a. the cross point storage array comprises a non-linear conductor proximate to at least one cross point storage location, and

b. the control logic comprises two or more transistor types wherein the transistor types comprise:

i. an NMOS type transistor and a PNP type bipolar transistor, but not a PMOS type transistor, or

ii. a PMOS type transistor and an NPN type bipolar transistor, but not an NMOS type transistor,

wherein a body of the non-linear conductor and a body of the bipolar transistor are defined by the same process step.

2. The integrated electronic memory device of claim 1 wherein the process step is a lithography step.

3. The integrated electronic memory device of claim 2 wherein the type of lithography is one of photolithography, imprint lithography, e-beam lithography or direct-write lithography.

4. The integrated electronic memory device of claim 1 wherein the process step that defines the body of the non-linear conductor and the body of the bipolar transistor does not also define the body of the NMOS type or PMOS type transistor.

5. The integrated electronic memory device of claim 1 wherein the process step is an etch step.

6. The integrated electronic memory device of claim 1 wherein the process step is a deposition step.

7. The integrated electronic memory device of claim 6 wherein the deposition step is either a CVD step or an epi growth step.

8. The integrated electronic memory device of claim 1 wherein the non-linear conductor is a diode, a base-emitter junction of a bipolar transistor, a base-collector junction of a bipolar transistor, or a vertically constructed MOS transistor.

Assignments (9)