Diagonal connection storage array
View Patent ↗In one aspect, an electronic memory array includes overlapping, generally parallel sets of conductors, and includes storage elements near each point of overlap. One set of conductors has a non-negligible resistance. An address path for each storage element traverses a portion of one each of the first and second sets of conductors and a selectable resistance element. All storage element address paths have substantially equivalent voltage drops across the corresponding storage elements.
1. An electronic memory array comprising:
a first plurality of generally parallel conductors each having a non-negligible resistance;
a second plurality of generally parallel conductors, each having a non-negligible resistance, overlapping the first plurality of generally parallel conductors;
a plurality of storage elements each disposed proximate a point of overlap between the first and second pluralities of generally parallel conductors;
one or more first power busses (i) generally parallel to the second plurality of generally parallel conductors and (ii) each having a non-negligible resistance; and
one or more second power busses (i) generally parallel to the first plurality of generally parallel conductors and (ii) each having a non-negligible resistance
wherein an address path for each storage element (i) is unique and (ii) traverses at least a portion of one of the first plurality of generally parallel conductors, at least a portion of one of the second plurality of generally parallel conductors, at least a portion of one of the first power busses, and at least a portion of one of the second power busses, and all storage element address paths have substantially equivalent voltage drops across the corresponding storage elements.
2. The electronic memory array of claim 1 , wherein each first power bus receives, at one end only, voltage from a first voltage source, a voltage potential on the first power bus decreasing with increasing distance from the first voltage source, and wherein the first power bus supplies power to the first plurality of generally parallel conductors.
3. The electronic memory array of claim 2 , wherein each second power bus receives, at one end only, voltage from a second voltage source, a voltage potential on the second power bus decreasing with decreasing distance from the second voltage source, and wherein the second power bus supplies power to the second plurality of generally parallel conductors.
4. The electronic memory array of claim 3 , wherein first and second voltage sources are disposed at diagonally opposite corners of the electronic memory array.
5. The electronic memory array of claim 1 , wherein the storage element is at least one of a fuse, an antifuse, a phase change material, and a programmable field-emitter element.
6. The electronic memory array of claim 2 , further comprising a first driver for receiving power from the first power bus and supplying power to one of the first plurality of generally parallel conductors.
7. The electronic memory array of claim 6 , wherein the first driver comprises a field-effect transistor.
8. The electronic memory array of claim 3 , further comprising a second driver for receiving power from the second power bus and supplying power to one of the second plurality of generally parallel conductors.
9. The electronic memory array of claim 8 , wherein the second driver comprises a field-effect transistor and a signal sense circuit.
10. The electronic memory array of claim 9 , wherein the signal sense circuit determines a state of the storage element at by sensing at least one of a current through and a voltage on the storage element.
11. The electronic memory array of claim 3 , further comprising a first driver on a first side of the electronic memory array and a second driver on a second, opposite side of the electronic memory array, the first and second drivers providing power to the first plurality of generally parallel conductors, wherein the second voltage source is connected to a first end of the second power bus when the first driver is active and to a second end of the second power bus when the second driver is active.
12. The electronic memory array of claim 2 , further comprising a first driver on a first side of the electronic memory array and a second driver on a second, opposite side of the electronic memory array, the first and second drivers providing power to the second plurality of generally parallel conductors, wherein the first voltage source is connected to a first end of the first power bus when the first driver is active and to a second end of the first power bus when the second driver is active.
13. The electronic memory array of claim 2 , wherein the first power bus has a resistivity per unit length approximately equal to that of one of the second plurality of generally parallel conductors.
14. The electronic memory array of claim 3 , wherein the second power bus has a resistivity per unit length approximately equal to that of one of the first plurality of generally parallel conductors.
15. A method for addressing a storage element in an electronic memory array, the method comprising:
selecting one of a first plurality of generally parallel conductors each having a non-negligible resistance;
selecting one of a second plurality of generally parallel conductors, each having a non-negligible resistance, overlapping the first plurality of generally parallel conductors;
supplying power to the first plurality of generally parallel conductors with one or more first power busses;
supplying power to the second plurality of generally parallel conductors with one or more second power busses; and
addressing one of a plurality of storage elements each disposed proximate a point of overlap between the first and second pluralities of generally parallel conductors,
wherein an address path for each storage element (i) is unique and (ii) traverses at least a portion of one of the first plurality of generally parallel conductors, at least a portion of one of the second plurality of generally parallel conductors, at least a portion of one of the first power busses, and at least a portion of one of the second power busses, and all storage element address paths have substantially equivalent voltage drops across the corresponding storage elements.
16. The method of claim 15 , wherein each first power bus receives, at one end only, voltage from a first voltage source, a voltage potential on the first power bus decreasing with increasing distance from the first voltage source.
17. The method of claim 16 , wherein each second power bus receives, at one end only, voltage from a second voltage source, a voltage potential on the second power bus decreasing with decreasing distance from the second voltage source.
18. The method of claim 17 , wherein first and second voltage sources are disposed at diagonally opposite corners of the electronic memory array.
19. The method of claim 15 , wherein the storage element is at least one of a fuse, an antifuse, a phase change material, and a programmable field-emitter element.
20. The method of claim 16 , further comprising switching the voltage received from the first voltage source from a first end of the first power bus to a second end of the first power bus based on a received column address.
21. The method of claim 17 , further comprising switching the voltage received from the second voltage source from a first end of the second power bus to a second end of the second power bus based on a received row address.