Low cost high density rectifier matrix memory
View Patent ↗A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
1. An electronic memory device comprising a plurality of layers of memory circuitry disposed over a single substrate, wherein each layer of memory circuitry comprises a plurality of programmable storage locations, each layer of memory circuitry comprises decoding circuitry for addressing the plurality of programmable storage locations, and at least one programmable storage location in at least one layer of memory circuitry comprises a phase-change material.
2. The electronic memory device of claim 1 , wherein the phase-change material comprises a chalcogenide.
3. The electronic memory device of claim 1 , wherein the single substrate comprises an insulating material.
4. The electronic memory device of claim 1 , wherein the single substrate comprises at least one of memory controller circuitry, error detection and correction circuitry, data decryption circuitry, data encryption circuitry, or a microprocessor.
5. An electronic memory device comprising:
a plurality of stacked layers disposed over a single substrate, each layer comprising:
a plurality of row storage lines;
a plurality of column storage lines overlapping the plurality of row storage lines;
a plurality of storage locations, wherein each storage location is disposed proximate to a point of intersection between a row storage line and a column storage line;
a plurality of nonlinear storage elements, wherein each nonlinear storage element is disposed at a storage location; and
decoding circuitry for addressing the plurality of storage locations,
wherein at least one nonlinear storage element comprises a phase-change material.
6. The electronic memory device of claim 5 , wherein the phase-change material comprises a chalcogenide.
7. The electronic memory device of claim 5 , wherein each nonlinear storage element comprises a diode.
8. The electronic memory device of claim 5 , wherein the single substrate comprises an insulating material.
9. The electronic memory device of claim 5 , wherein the single substrate comprises at least one of memory controller circuitry, error detection and correction circuitry, data decryption circuitry, data encryption circuitry, or a microprocessor.
10. An electronic memory device comprising:
a plurality of layers of memory circuitry, wherein each layer of memory circuitry comprises a plurality of storage locations and decoding circuitry for addressing the plurality of storage locations; and
a first memory controller disposed beneath the plurality of layers of memory circuitry and interconnected to at least one of the layers of memory circuitry.
11. The electronic memory device of claim 10 , further comprising a second memory controller disposed beneath the plurality of layers of memory circuitry and interconnected to at least one of the layers of memory circuitry.
12. The electronic memory device of claim 11 , further comprising a substrate disposed beneath the plurality of layers of memory circuitry, the substrate comprising the first memory controller and the second memory controller.
13. The electronic memory device of claim 10 , further comprising a substrate disposed beneath the plurality of layers of memory circuitry, the substrate comprising the first memory controller.
14. The electronic memory device of claim 13 , wherein the substrate comprises an insulating material.