Multiple sector parallel access memory array with error correction
View Patent ↗The present invention is a method for accessing more than one block of correctable information at a time when it is most efficient to access more bits of information at a time on a given dimension, for example from a multiple bit per cell (MLC) memory element, than the error correction algorithm can correct. Since it may be more efficient to access more bits of information at a time on a given dimension than the error correction algorithm can correct, that access is performed in this most efficient way, but the information is divided into correctable blocks within this information such that the error correction algorithm can still compensate for a serious fault along a given dimension. Furthermore, the present invention can be employed even when the number of bits retrieved along a given dimension is less than the number of correctable bits when it is desired to protect against a given number of faults which could, in total, exceed the number of correctable bits.
1. A method for accessing a memory array comprising:
grouping bits for error correction such that (i) bits obtained by accessing a multiple bit-per-cell memory element having at least two bits at a row address and a column address are divided across two groupings and (ii) fewer bits from the multiple bit-per-cell memory element are included in any grouping able to be corrected using an error-correcting algorithm;
receiving a data-access request to access a first bit in the multiple bit-per-cell memory element, the first bit belonging to a first grouping;
accessing all of the bits in the multiple bit-per-cell memory element, wherein a second bit in the multiple bit-per-cell memory element belongs to a second grouping different from the first grouping; and
storing the first and second bits in at least one buffers,
thereby avoiding having to re-access the row address and column address at a later point in time to access the second bits.
2. The method of claim 1 whereby said grouping is performed in the controller.
3. The method of claim 1 whereby said grouping is performed in the memory chip.
4. The method of claim 1 whereby the buffer is implemented in hardware.
5. The method of claim 1 whereby the buffer is a virtual buffer implemented in software.
6. The method of claim 1 whereby the multiple bit-per-cell memory element comprises bits in a 3-D stack.
7. A memory device whereby bits are grouped for error correction such that (i) bits obtained by accessing a multiple bit-per-cell memory element having at least two bits at a row address and a column address are divided across two groupings and (ii) fewer bits from the multiple bit-per-cell memory element are included in any grouping able to be corrected using an error-correcting algorithm, wherein the memory device comprises a plurality of buffers and wherein, in response to a data-access request to access a first bit belonging to a first grouping in the multiple bit-per-cell memory element, wherein all of the plurality of bits in the multiple bit-per-cell memory element are accessed, the first bit in the plurality of bits corresponding to the first grouping and a second bit in the plurality of bits corresponding to a second grouping different from the first grouping, and stored in the buffers such that each buffer stores bits corresponding to different groupings, thereby avoiding having to re-access the row address and column address at a later point in time to access the second.
8. The device of claim 7 whereby said grouping is performed in the controller.
9. The device of claim 7 whereby said grouping is performed in the memory chip.
10. The device of claim 7 whereby the buffers are is implemented in hardware.
11. The device of claim 7 whereby the buffers are is virtual buffers implemented in software.
12. The device of claim 7 whereby the multiple bit-per-cell memory element comprises bits in a 3-D stack.
13. A memory system comprising a controller and a memory chip whereby bits obtained by addressing a multiple bit-per-cell memory element at a row address and a column address and comprising an addressable plurality of bits are grouped such that fewer bits are included in a group from a given element than can be corrected given an error correction algorithm, wherein the memory device comprises a plurality of buffers and wherein, in response to a data-access request to access a first bit in the plurality of bits belonging to a first grouping in the multiple bit-per-cell memory element, all of the bits in the multiple bit-per-cell memory element are accessed, the first bit corresponding to the first grouping and a second bit in the plurality of bits corresponding to a second grouping different from the first grouping and stored in the buffers such that each buffer stores bits corresponding to different groupings, thereby avoiding having to re-access the row address and column address at a later point in time to access the second bits.
14. The system of claim 13 whereby said grouping is performed in the controller.
15. The system of claim 13 whereby said grouping is performed in the memory chip.
16. The system of claim 13 whereby the buffers are is implemented in hardware.
17. The system of claim 13 whereby the buffers are is virtual buffers implemented in software.
18. The system of claim 13 whereby the multiple bit-per-cell memory element comprises bits in a 3-D stack.